EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: BroMarduk on February 02, 2021, 03:51:24 am
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I recently decided to try building my first device and I wanted to give it a push on/hold off latching power switch. I found a rather good example here: http://www.mosaic-industries.com/embedded-systems/microcontroller-projects/electronic-circuits/push-button-switch-turn-on/switching-battery-power. (http://www.mosaic-industries.com/embedded-systems/microcontroller-projects/electronic-circuits/push-button-switch-turn-on/switching-battery-power.) I put it on a breadboard, tweaked it a bit, and I got the circuit to do what I want it to do with one exception described below. Here is the schematic:
[attach=1]
The way it is supposed to work is that J1 dictates the start-up behavior of the circuit. If J1 is connected to V+, when applying initial power, the switch should start up open. When J1 is connected to ground, the switch should start up closed. This works as expected when applying initial power and I get the behavior that I expect depending on the position of J1. The problem I am having is when J1 is connected to ground and I shut down using the long button press. This works as expected and the circuit shuts off power from D2 after holding it down for three seconds and all is good. After shutting it down this way, if I disconnect the power lead and quickly plug it back in, I expect the switch to start up closed (due to the J1 position), but it does not, it starts up opened. My guess is this is because C2 is still supplying voltage to G2 on the MOSFET. If I wait about 30 seconds OR press S1 momentarily (or short G2/S1) then plug in the power lead again, G2 is below the 0.7V gate threshold and it works as expected.
Based on the above behavior, I’m thinking the best way to solve the problem is to pull G2 to ground when the circuit loses power, but my limited brain just can’t figure out the simplest way to make that work (or if that is even the cause of the problem).
(Updated with correct gate information)
Am I way off base here?
Thanks in Advance,
Dan
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Not an answer to your question, but in other discussions of the Mosaic latching power switch circuits push-button controllers such as the LTC2955 came up:
https://www.analog.com/media/en/technical-documentation/data-sheets/2955fa.pdf (https://www.analog.com/media/en/technical-documentation/data-sheets/2955fa.pdf)
In particular, it implements the long-press to turn off protocol.
Another idea is to put the Adalogger into a low power state in which it draws micro-amps. It can still monitor a push button to wake up.
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...The problem I am having is when J1 is connected to ground and I shut down using the long button press. This works as expected and the circuit shuts off power from D2 after holding it down for three seconds and all is good. After shutting it down this way, if I disconnect the power lead and quickly plug it back in, I expect the switch to start up closed (due to the J1 position), but it does not, it starts up opened.
I've simulated and tested that particular scenario as you've mentioned but the circuit performs correctly (see attached image). I tried disconnected the supply for 0.2,1,2,4 and 8 seconds. When reconnected, the circuit powers ON regardless. I've also simulated near immediate supply interruption after user button release but result is still the same.
In your circuit, you definitely don't need two 1N4148 diodes and you've to lower the NMOS gate resistor 270K value to get a reliable operation. Perhaps a small load on the output is good too.
[attachimg=1]
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When the circuit is off, the output cap C3 is discharged and the switch cap C1 is discharged. C2 will be charged with a time constant of 10 ms through R2 and the input voltage source. However, if you disconnect the power source, C2 has no means to discharge. When the power is reconnected C2 is still charged up and drives the gate of Q1 high turning off the circuit.
So why are your unplugging the power source? If you are unplugging it to simulate a power failure this is not a realistic scenario since the power would go down with the unit still connected. If momentarily unplugging the power source is an expected event then this must be accommodated.
You should be able to put a high value resistor across C2 to drain the charge when the power cable is disconnected. I would worry that 1 Meg can maintain the gate at too low a voltage and potentially cause a malfunction. 4.7 Meg should be very safe with only 0.125V between gate and source. Even 2 Meg should work ok with about 0.3V. The time constant of draining the cap will then be around 0.47 sec. So if the power is unplugged for for even just 200 ms the unit should power up when plugged back in.
You also could add the resistor across the power input instead. Both ways drain the same current when the unit is powered but off, but across the input it won't have any effect on the operation so the resistor could be smaller. Will a couple of uA constant drain be an issue?
I didn't simulate this because it would require getting a model for the transistors and adding that to LTspice which is just too big a PITA. Let us know if it works like I think.
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...The problem I am having is when J1 is connected to ground and I shut down using the long button press. This works as expected and the circuit shuts off power from D2 after holding it down for three seconds and all is good. After shutting it down this way, if I disconnect the power lead and quickly plug it back in, I expect the switch to start up closed (due to the J1 position), but it does not, it starts up opened.
I've simulated and tested that particular scenario as you've mentioned but the circuit performs correctly (see attached image). I tried disconnected the supply for 0.2,1,2,4 and 8 seconds. When reconnected, the circuit powers ON regardless. I've also simulated near immediate supply interruption after user button release but result is still the same.
In your circuit, you definitely don't need two 1N4148 diodes and you've to lower the NMOS gate resistor 270K value to get a reliable operation. Perhaps a small load on the output is good too.
(Attachment Link)
Nice simulation, but he is talking about disconnecting the power source. To simulate that will require the addition of a switch on the input. I think you will see the behavior he described if you do that.
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Nice simulation, but he is talking about disconnecting the power source. To simulate that will require the addition of a switch on the input. I think you will see the behavior he described if you do that.
Silly me, that was a stupid mistake on my part. Indeed the circuit failed to operate as OP stated. This is the same scenario as having an input electrolytic capacitor, which stores charges even if the power source is briefly disconnected.
I can offer no simple solution but if OP are using a DC jack socket with three terminals to get the power, then it is possible to connect a small value resistor of several Kohms across the supply via the DC jack socket switching mechanism when user remove the jack. Once you have remove the DC plug, the resistor would discharge the input capacitor via this resistor. I've done the simulation again with this resistor and indeed the circuit now works.
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Not an answer to your question, but in other discussions of the Mosaic latching power switch circuits push-button controllers such as the LTC2955 came up:
https://www.analog.com/media/en/technical-documentation/data-sheets/2955fa.pdf (https://www.analog.com/media/en/technical-documentation/data-sheets/2955fa.pdf)
In particular, it implements the long-press to turn off protocol.
Another idea is to put the Adalogger into a low power state in which it draws micro-amps. It can still monitor a push button to wake up.
There are multiple ways to do this and the LTC2955 or one of the variants would most likely work, but there is a cost difference which is a consideration.
The Adalogger is just a placeholder for any powered circuit and the device I want to build and power would not have the microcontroller - this was just a quick way for me to test and get some load on the circuit.
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Nice simulation, but he is talking about disconnecting the power source. To simulate that will require the addition of a switch on the input. I think you will see the behavior he described if you do that.
The case here is when the user shuts down the device and changes a battery in less than the discharge time of the capacitor. It's a fringe case and I could operate with the limitation, but in my quest for learning, I wondered if it could be solved in a simple manor. Well, maybe not simple for me.
My thoughts were around how do I keep a path (G2 to ground) open when power present, but then close it when power disappears, but I don't know how to do that or even if I would be introducing additional undesired side effects by doing so. I'm going to give the 2M resistor a shot today...
In any case, thanks for responding.
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I've simulated and tested that particular scenario as you've mentioned but the circuit performs correctly (see attached image). I tried disconnected the supply for 0.2,1,2,4 and 8 seconds. When reconnected, the circuit powers ON regardless. I've also simulated near immediate supply interruption after user button release but result is still the same.
In your circuit, you definitely don't need two 1N4148 diodes and you've to lower the NMOS gate resistor 270K value to get a reliable operation. Perhaps a small load on the output is good too.
Thanks for taking a look. I also tried simulating it at http://falstad.com/circuit/circuitjs.html (http://falstad.com/circuit/circuitjs.html) with the attached file (still learning LTSpice). I had to play with the resistor values a bit in the breadboard and simulator (mostly in the simulator), but it pretty much shows the same thing as the real circuit. The breadboarded circuit is much more consistent, but I can see the same general effects in the simulator.
The original circuit called for a BAV99 which I determined to be the equivalent of two 1N4148's, but yes, it does work fine with just one.
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The original circuit doesn't consume any energy when the load is switched off. Therefore the charge on the input side would take a very long time to drain away. If you do anything to drain the charge when the power is removed, this would mean an extra continuous loading on the battery, albeit a few microamps even with the load switched off.
It is like a problem with a charged capacitor. How does one briefly discharge the capacitor when the power is removed, but the discharge circuit must consume no energy if the power is connected?
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You should be able to put a high value resistor across C2 to drain the charge when the power cable is disconnected. I would worry that 1 Meg can maintain the gate at too low a voltage and potentially cause a malfunction. 4.7 Meg should be very safe with only 0.125V between gate and source. Even 2 Meg should work ok with about 0.3V. The time constant of draining the cap will then be around 0.47 sec. So if the power is unplugged for for even just 200 ms the unit should power up when plugged back in.
You also could add the resistor across the power input instead. Both ways drain the same current when the unit is powered but off, but across the input it won't have any effect on the operation so the resistor could be smaller. Will a couple of uA constant drain be an issue?
I tried the first method (4.7M across C2) and that did pull the gate to ground fairly quickly, but had the side effect of not turning the circuit off until you released the button switch (normally the circuit will shut off while holding down the button after 3 seconds.) With the resistor in place you had to wait 3 seconds, then release the button.
Then I tried the 4.7M from G2 to ground and that had the desired effect all the way around, but I will have to measure the current draw when the circuit is off but powered. A few uA will not matter with 4AA or a 9V battery. I will also test the resistor across the power terminals as well and do some math and see if either option is viable. This would by far be the simplest solution.
Thanks for the help.
Thanks for all the help.
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The original circuit doesn't consume any energy when the load is switched off. Therefore the charge on the input side would take a very long time to drain away. If you do anything to drain the charge when the power is removed, this would mean an extra continuous loading on the battery, albeit a few microamps even with the load switched off.
A uA or five is fine for my purposes, mA on the other hand would be bad for battery life.
It is like a problem with a charged capacitor. How does one briefly discharge the capacitor when the power is removed, but the discharge circuit must consume no energy if the power is connected?
I guess my secondary goal was to try and figure out how to solve that exact problem. Something that holds the circuit open when powered and then closed when power is removed. It's the complicated way (to me), but may be appropriate depending on how much current the resistor is sinking.
If anyone can point me in the right direction here, that would be appreciated if for nothing else but increasing a poor beginner's knowledge.
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I have not tried a simulation, but my mental analysis was that C2 is the only capacitor charged when power is off. However, that is not completely true. C1 is also charged when the unit is first turned off, however it quickly discharged with an RC of 0.1 seconds. Then C2 is the only cap charged after the unit is off for a fraction of a second.
Once power is disconnected, C2 would have to be the power source for draining C2. If you added a pFET across C2 with source at G2, drain to a resistor to GND and gate to the DC input, i think that will drain C2 only when power fails. I don't know if this will be much of an improvement however. It only takes a small current to drain C2 and most FETs will have enough leakage current to not be very different from 4.7Meg.
BTW, for the purpose of draining C2 the resistor at the power input and across C2 are the same since the power input is connected to C2 by the 100k resistor. The only difference is when across the input it has no other impact than drawing a very small current while across C2 directly it forms a voltage divider with the 100k R2 and so must be much larger to not disrupt the function of the circuit.
It seems a shame to disrupt the operation of this circuit with this resistor. Otherwise the circuit has virtually no power drain when off. However, since the two FETs have leakage current, there will always be a tiny current involved.
Almost forgot. I can't see a reason for the resistor to cause the change in behavior you mention. C2 is not involved in turning off the unit. That happens through D1 (really should be just one diode and that should be a Schottky which I think the BAT is) pulling low on C3 through R3. The RC of 2.7 secs is what sets the off delay and should turn the unit off without releasing the button by C2 charging up through the 100k R2 once G1 has pulled sufficiently low as to release G2. In this case C1 and C2 are in parallel so that time constant is 1.1 uF * 100k or 0.11 sec. I suggest you get to the bottom of the behavior you are seeing. Perhaps it is because you used a 2Meg resistor rather than 4.7Meg?
I'm busy today, but later i may have time to simulate this. I'll need to add a switch to the power input which is a bit clumsy.
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What about a diode from G2 to 6VDC? When power is disconnected, the capacitor would discharge through the diode to the 6V line as it sinks to ground through R1+R2. But in normal operation it would have no effect. Kinda like a GPIO protection diode.
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Almost forgot. I can't see a reason for the resistor to cause the change in behavior you mention. C2 is not involved in turning off the unit. That happens through D1 (really should be just one diode and that should be a Schottky which I think the BAT is) pulling low on C3 through R3. The RC of 2.7 secs is what sets the off delay and should turn the unit off without releasing the button by C2 charging up through the 100k R2 once G1 has pulled sufficiently low as to release G2. In this case C1 and C2 are in parallel so that time constant is 1.1 uF * 100k or 0.11 sec. I suggest you get to the bottom of the behavior you are seeing. Perhaps it is because you used a 2Meg resistor rather than 4.7Meg?
I went back and tried again based on your assurance and yes, it does work correctly with a 2M or 4.7M resistor. I agree it should have worked the first time. I have not been able to recreate the issue, so I may have bumped a component on the breadboard while inserting the resistor and shorted something. Regardless, I can't duplicate the behavior now. Sorry about that.
The diode specified in the circuit is a BAV99 which is a rectifying diode array (hence why I used two in the original design). Is a Schottky a better choice in this circuit?
I'm busy today, but later i may have time to simulate this. I'll need to add a switch to the power input which is a bit clumsy.
Thanks for the offer, but I think I have this circuit in a good place and your advice has been very sound (still curious about the Schottky diode). I want to try the p-Channel MOSFET and measure the current that way (and check the behavior) mostly for my own knowledge (hopefully one day I'll be able to do as thorough of a mental analysis on a circuit as you did), but also want to compare the constant leakage current of the MOSFET vs. the current the resistor pulls when powered off. The MOSFETs I am using have a ±1uA IDSS and ±0.1 IGSS leakage and considering the device will be off but still 'powered' most of the time. Still, even with a 400mAh 9V battery, it's going to last a long time, even if it ends up drawing 3.7uA or so...
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What about a diode from G2 to 6VDC? When power is disconnected, the capacitor would discharge through the diode to the 6V line as it sinks to ground through R1+R2. But in normal operation it would have no effect. Kinda like a GPIO protection diode.
Definitely worth a shot, but it didn't seem to have a good path to ground.
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The BAV99 diode may have two in the package, but you can use just one. Each one will have up to 0.7V depending on the current. Even with two diodes they eventually will pull the gate low enough to turn it off, but the last bit will be slower than the simple RC time constant would predict. A FET is not like a relay, either all on or all off. Given Q1 is only pulling a very low current through the drain (60 uA max) even a modest voltage on the gate will keep Q2 on. So go with one diode and a Schottky is better, but probably not required. It's just that Q1 doesn't even need to pull 20 uA through R2 to turn on Q2, that doesn't take much voltage across G1 to S1. The FETs you picked are very sensitive.
I think Peabody's idea is good, but I'm not sure how it would actually work. C2 would drain through R2 if the Vin had a ground path. The diode isn't needed really.
I would test a 2 and a 10 Meg resistor across the input. If both worked i would use the 4.7 Meg resistor and live with the 1.2 uA of additional current drain.
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I think Peabody's idea is good, but I'm not sure how it would actually work. C2 would drain through R2 if the Vin had a ground path. The diode isn't needed really.
What's needed is some point anywhere on the 6V side of things that quickly drops from about 6V to ground when the power is disconnected. It could even be downstream of the mosfets. Well, what about D2? It connects directly to the regulator, which has a ground terminal and a load. What happens there when you pull the plug?
That would leave the capacitor discharged to near ground regardless of the J1 setting. But is that what you want?
Edit: Looking at the schematic again, it seems to me that when the power is on, G2 is at ground, and the capacitors connected to it are discharged to ground. G2 is held there because the N-channel is on. If the P-channel doesn't stay on across a brief power interruption, I think it's because the N-channel has turned off, and won't turn back on again unless the P-channel has turned back on. Catch 22. So you would need to press the button. Well, I guess I really don't understand the circuit. Have you considered controlling all of this from an MCU GPIO pin instead?
Edit2: Sorry, I didn't read carefully enough. The power interrupt is AFTER you've powered down with a long press. So the caps are fully charged. Well, the diode to D2 won't work because then it would never turn off, or stay off. Sorry to go round and round on this. I shoulda stood in bed.
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Yeah, just to recap (pun intended :palm:) the cap C2 is connected between ground and G2 so that when power is initially applied it pulls down on G2 to fire up the output, aka power up in the on state. However, when the unit is off, C2 is charged up through R2 since G2 has to be high. If power fails R2 will also drain C2 through the 0V input in less than 10 ms so the circuit will operate normally when power is returned forcing the circuit ON. So a momentary glitch in power can turn the unit on.
A friend had a Hi-Fi... I mean a stereo... I mean an entertainment system (trying not to sound too old, but those things people used before iPods) that was pretty high wattage. it would get turned off with a remote after watching a movie or something. A power glitch in the middle of the night would power it up with the volume where it had been set at the end of the movie! Yeah, sleeping to standing up in 100 ms!!!
However, if the power is disconnected while the unit is in the OFF state, that OFF state is remembered by C2 being charged and the unit will NOT turn ON when power is reconnected. This can be fixed by adding a resistor to drain that current, preferably at the power input.
If a bit of current drain is not a problem, the power drain resistor, which we have been trying to make as large as possible to minimize the current, can be replaced by a LED draining more current, but doing something useful. It can be across the input to indicate the unit has power to it or the LED and resistor can be across C2. This would be a power OFF indicator however. Wiring it as a power ON indicator would not work to drain cap C2. The real issue is since the circuit draws no power from the input when off, there is no way to tell when power is disconnected without providing at least a very low OFF state leakage current.
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I would just say that God intended things to come up in the Off state when the battery is connected. You should have to push the button to turn it on. Anything else could be obnoxious (like that TV), and potentially even dangerous. So it seems to me the entire J1 thing is a bad idea, and what the OP wants is something he shouldn't want. Anyway, in case anyone might be interested in the future, I'll attach a way of controlling this with an MCU GPIO pin. The long press Off would be detected by the MCU, but have no other direct effect. And the button could be used for other input while the MCU is on.
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I would just say that God intended things to come up in the Off state when the battery is connected. You should have to push the button to turn it on. Anything else could be obnoxious (like that TV), and potentially even dangerous. So it seems to me the entire J1 thing is a bad idea, and what the OP wants is something he shouldn't want. Anyway, in case anyone might be interested in the future, I'll attach a way of controlling this with an MCU GPIO pin. The long press Off would be detected by the MCU, but have no other direct effect. And the button could be used for other input while the MCU is on.
Thanks for the comments and suggestions. It was probably lost in the thread that the eventual circuit will not be using a microcontroller, otherwise I would agree that using a microcontroller in a low(ish) power state solves the problem
And I don't disagree with you on the off state being the normal state for most things and God may have intended it :), but I do have a use case for the latter scenario (think of something that is a safety device that you would want to ensure faulted on the side of coming on). Deciding whether I should do something is different from how and what cost the decision will incur. The cost here is a bit over a uA and a resistor and solves one of my use cases but may not be the best solution for everyone.
The real issue is since the circuit draws no power from the input when off, there is no way to tell when power is disconnected without providing at least a very low OFF state leakage current.
This pretty much sums up the problem I was trying to solve and the answer. I didn't know if I had overlooked something like a diode or transistor that would be a better option for what I wanted for 'free'.
I actually learned a lot from everyone's comments and suggestions here, so thanks all!
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I would just say that God intended things to come up in the Off state when the battery is connected. You should have to push the button to turn it on. Anything else could be obnoxious (like that TV), and potentially even dangerous. So it seems to me the entire J1 thing is a bad idea, and what the OP wants is something he shouldn't want. Anyway, in case anyone might be interested in the future, I'll attach a way of controlling this with an MCU GPIO pin. The long press Off would be detected by the MCU, but have no other direct effect. And the button could be used for other input while the MCU is on.
I think you are being very judgemental... that's my judgement of you. ;)
This is a not uncommon issue in PCs. Following a glitch in power they don't come up in the power on state. But if the PC is being used as a server that should always be on unless it is turned off explicitly, then it needs to turn itself on.
This may not be the norm, but it is not uncommon.
The MCU approach is good.
The unit I'm presently working on has an MCU that stays on always even if only at µA levels (mcA levels if you are in the medical profession). However, because of the lack of reliability of software turning off the rest of the machine is mediated by the FPGA. The MCU requests the power be turned off and only if the MCU has been behaving will the FPGA turn the machine off, which includes itself. Once the FPGA is off obviously only the MCU can turn the rest of the machine on. I had to create a two transistor FF to retain the on/off state. A pair of transistors were added and capacitively coupled to outputs from the MCU and FPGA. To act each of the devices has to remove the tristate on the output (the default state), drive the output low for some minimum time (5 ms I think) then drive the output high. The 5 ms low time discharges the series cap so the gate can be pulled up. The capacitor also prevents the power on of the FPGA from accidentally turning the power off again.
It seems complex, but our requirements are unique. The point is the MCU is the guy driving the power state with a current consumption not much different from the 4.7 Meg resistor.
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Ok, I was out of line speaking for God. But I would just say that the OP said he wanted the power to be turned on automatically when there was a power interruption AFTER he had powered down with a long press. That's not the same as wanting it to stay on if there's a glitch while it's up and running, which I suspect it will do as originally configured, but it would be interesting to test that. In any case, it looks like the added resistor will give him what he wants.