Author Topic: PWM Demo Rev. 2  (Read 275 times)

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Offline SummerSausage52Topic starter

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PWM Demo Rev. 2
« on: December 01, 2025, 10:04:44 pm »
Schematic https://1drv.ms/b/c/aa0fe51966fc4036/IQBUHISteEUeSr6c0ApIEvjzAcCKUf-T6_J-0DHG0rGk5xY?e=sTuTfm

I made a post asking for feedback on a PWM Demo PCB I designed last week (https://www.eevblog.com/forum/beginners/pwm-demo-rev-1/). Being my first PCB, there was a lot wrong with it. I'm hoping I was able to make some improvements this time around. I've yet to order as I'd prefer to have the revision verified first. No big changes have been made to the PWM circuit.

Referenced Schematic for Duty Cycle Adjustment
https://theorycircuit.com/ic-555-ic-741/adjustable-duty-cycle-pwm-generator-circuit/

PCB/Circuit Changes:
  • Removed NPN BJT for switching frequency and left SW1 in full control of switching C3 in and out of parallel with U1-2/6
  • Switched out barrel jack 12VDC for USB micro B 5VDC; I mostly imagine auxiliary output being used for controlling a fan or motor PWM and I believe 5V is more common than 12V for PWM signaling.
  • Added C4 for high frequency filtering for U1-VCC
  • Added TP1-6 (functions explained in schematic)
  • Swapped out 100nF electrolytic caps with ceramic ESR caps (104)
  • Removed second auxiliary output (pin headers); If I need dupont, I have ferrule-to-dupont wires made.

Schematic Changes:
  • Added color-coding and sub-circuit descriptions
  • Added waveforms, voltages, and current readings (derived from LTspice simulation)
  • Added power dissipation table for resistors, current table for easily readable current highs on most devices, testpoints ID table

I used Andrew Greenberg's Checklist for Schematics (https://docs.google.com/document/d/1gCPILcrdGZJjRzIDSL-b3ezVReeK5S-7raeub1RohyE/edit?tab=t.0#heading=h.gjdgxs) to give me a better idea of what was missing as well as the feedback I got on EEVblog and here. Thank you!


« Last Edit: December 01, 2025, 10:11:00 pm by SummerSausage52 »
 

Offline Infraviolet

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Re: PWM Demo Rev. 2
« Reply #1 on: December 03, 2025, 02:08:57 am »
If we ASSUME that the circuit schematic is correct and focus solely on the board design:

Well really with a 555 timer the application isn't too demanding, minor details of the board's layout should affect functionality much.

I would note that if C1 and C2 are decoupling capacitors (or if either of them is such) for the 555 then you want to make the traces between them and the 555's power pins as direct as possible, and avoid having them go up and down through vias, just a straight trace from package power pin to capacitor. If they are not decoupling caps then you must add one, I usually use an 0603 10uF ceramic MLCC, but they might only be available in SMD and it looks like you are sticking to through hole for this design. But a 100nF ceramic with through hole legs would do ok for a decoupling cap too. Decoupling is necessary for all IC chips, but particularly for something like a 555 which throws an output up and down between the rails and has some relatively old fashioned (prone to momentary current shoot through) circuitry inside. Some decoupling needs an electrolytic (large capacitance but slower to react) capacitor as well, but all deocupling needs a ceramic (smaller capacitance but provides a local reservoir of charge which can react almost instantly to smooth out glitches). The decoupling cap must be close to the IC, in your design and for a 555 where pins 1 and 8 are the power pins a good place to put it would be just above the 555.

I would personally put labels for my off-the-board pins on both sides of the board. So each pin of a header and each pad which might go to a lone wire should have a label beside it, both on the bottom and the top.

TP2,3,4,5, and 6 all should be wired to somewhere, otherwise why include them?

It's a personal choice again, but to make assembling boards by hand easier I like to put component values and other descriptions beside them in the silkscreen, so the board literally says on it 100n beside a 100nF cap or 5K6 beside a 5.6K ohm resistor. One has to be a little careful with this if a board design features components which have the same value but a different rating in some other fashion, like if you had some 10uF ceramic capacitors where some had to be rated for 25V but others only needed to cope with 6V. But I don't think in your simple design, where everything is powered from 5V anyway, that you're going to have any components of the same value but where other properties differ.

Here's a few other things I tend to have on my "Is this PCB ready to order yet" dhecklist:

1. All traces placed

6. Silkscreen not overlapping pads or vias too badly (any silkscreen which does overlap won't get printed)
7. All pinouts labelled
8. Board version number included (include a "version 3" or "revision D" or "date of design completion Nov 30th 2024" on a board's silkscreen somewhere, a name for the board is also good to include)
9. All silkscreen value designators lined up to correct component (move and check where line goes)

11. No traces closer than 0.6mm to board edges (ideally still further than that)

14. Vias not too close to soldering points of other signals
15. Vias underneath components suitably far away from where solder will be applied on other signal's pins
16. Height clearances checked in 3d cad for locations of tall components

19. Clear markings for all polarised parts (your choice of the markings for your diodes is one such example, it's not the only way to represent diode polarity but it's a perfectly understandable one still)

23. Double check direction of any headers which take polarised connectors (the type which cannot be plugged in the wrong way round, such as Molex Picoblade cables)

31. Ensure no places where a trace enters a via and then leaves it from another side on the same layer, always have the continuing trace run past the via and the via off on a little side spur (this one might not be so necssary for wider traces and larger vias, but for small traces and small vias there is the risk that if the via hole gets drilled a bit off centre then it can actually end up breaking a trace which runs in to one side of the via then out of the other)

37. If the board has mounting holes for screws to go through then either only ground planes should be under screw head areas, or no copepr at all should be in these areas (this can change if you've got systems where you specifically want to use a certain screw to share a ground with an equipment chassis or something, but for most boards you just want to make sure the metal screw head doesnt short anything out)
« Last Edit: December 03, 2025, 02:14:01 am by Infraviolet »
 

Offline SummerSausage52Topic starter

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Re: PWM Demo Rev. 2
« Reply #2 on: December 04, 2025, 12:19:19 am »
Thanks for the feedback! I have linked the schematic at the top of the post and I am also looking for critique on that. I wasn't able to include a picture of it for whatever reason, probably because the file size was too big?

C1 and C4 are decoupling for CV and VCC respectively and I will look into getting them closer and avoiding vias; since there is a ground plane, I won't need to worry about distance from ground, or is that something that I'd have to worry about even without the ground plane?

The testing points were the last thing I added before posting and I was pretty tired, so I think I just forgot to connect them. They are connected in the schematic. For the screw terminal, I still need to add positive and negative labels. C2 is connected to NE555-2/6 and is where frequency is derived from. Hence switching C3 into that part of the circuit lowers the frequency by around 100Hz. This is by design.

I do still need to add version and name info to the board. I plan on doing that when I'm happy with this revision and it has been thoroughly peer reviewed.

I will save your checklist items for future designs. Thank you for including it!
 

Offline Alien Brother

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Re: PWM Demo Rev. 2
« Reply #3 on: December 04, 2025, 04:05:12 am »
Personally, I'd use large SMD parts instead of through hole; 1206 is okay to solder and saves money on board size. Otherwise, through hole resistors can also come in smaller cases, there can be a smaller 10u cap, etc. I'd also check that annular ring size on SW1,2 is what you're fine with (for me, 0.35mm or so minimum). Routing wise, there are probably things to optimize. For example, traces from R2 and R3 seem to go to the other edge of the board.
« Last Edit: December 04, 2025, 04:39:26 am by Alien Brother »
 

Offline SummerSausage52Topic starter

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Re: PWM Demo Rev. 2
« Reply #4 on: December 06, 2025, 02:53:50 pm »
I've worked with the same footprint and component in the past for SW1/2 so I shouldn't have any issues there. I want to get into SMD, but I was hoping to get this version in a good place before making further adjustments. The board size is still in the cheapest tier for JLCPCB right now, but I would like to get it pretty small once I have everything up to par. It would be really cool if I could have a smaller and smallest version to test my soldering and reflow techniques. I believe I could swap out the 50V 10uF cap for a 25V and that'd be fine. I don't quite remember why I used a 50V in the first place, but I suppose that's what this drafting phase is for. I will definitely look into optimizing R2 and R3 paths better. Thank you so much for the feedback!
 


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