Author Topic: PWM dimmers and supply line noise  (Read 2136 times)

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Offline iroc86

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PWM dimmers and supply line noise
« on: March 27, 2021, 01:12:51 pm »
What are some filtering methods to remove supply line noise caused by a PWM circuit?

I am testing two LED dimmer circuits to drive a 24 V, 1.3 A load:

  • Cheap eBay/Amazon dimmer; 555 timer + op amp, low-side MOSFET switch, 1.4 kHz
  • Modified version of above; op amp swapped for comparator, 11 kHz, added gate driver for higher-frequency operation (schematic attached below)

Both of these circuits produce noise on the 24 V supply line. It's worse with the 11 kHz version (~6 Vpp). If I add a 100 µF capacitor across the 24 V rail--at the circuit--the noise is greatly reduced, but the spikes remain at the supply itself. I have tried a few general-purpose SMPSes, as well as my HP bench lab supply. Same effect. Waveforms attached below.

I'm pretty sure that I need better filtering at the input, perhaps with a choke, but I'm not sure how to size the components. I'm also confused as to why the supply terminals still have noise, even with the 100 µF cap, when the voltage spikes at the circuit itself are greatly reduced. Am I picking up radiated noise via the supply leads? Seems unlikely, but neither of the these circuits are shielded.

Looking for some advice on a path forward. Thanks! :)
 

Offline Algoma

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Re: PWM dimmers and supply line noise
« Reply #1 on: March 27, 2021, 02:06:48 pm »
I think Dave had a video a while ago about reducing power supply noise that would very much apply here.

https://youtu.be/wopmEyZKnYo
« Last Edit: March 27, 2021, 02:11:26 pm by Algoma »
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #2 on: March 28, 2021, 01:09:10 am »
I think Dave had a video a while ago about reducing power supply noise that would very much apply here.

https://youtu.be/wopmEyZKnYo

Thanks for the link, but I'm not sure that really applies to my situation. I'm not wanting to reduce ripple on a PWM output, but rather eliminate the the noise (interference) that the PWM circuit puts on the main supply rail. The input to the circuit is clean and doesn't require filtering. Dave's video is more about filtering the output of DC-DC converters. I think the noise in my circuit is being caused by the high-frequency switching of the MOSFET. Am I perhaps missing something in the video?
 

Offline Algoma

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Re: PWM dimmers and supply line noise
« Reply #3 on: March 28, 2021, 02:22:22 am »
At about the 9 minute mark Dave mentions the use of the RC circuit along with the Capacitance multiplier to filter PWM output into linear DC.

While an RC filter with Capacitive multiplier will suppress ripple, The other option is an LC filter, using an Inductor to suppress those voltage spikes.. You're basically building an output side of your own switch mode power supply.
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #4 on: March 28, 2021, 02:13:21 pm »
At about the 9 minute mark Dave mentions the use of the RC circuit along with the Capacitance multiplier to filter PWM output into linear DC.

But if I filter my PWM signal into linear DC, then I don't have a PWM signal anymore to drive the MOSFET :). Or, are you suggesting to filter the 24 V rail using RC and LC topologies to block the PWM spikes?

I've been researching this issue a bit more and found some similar questions on StackExchange:

How to combat noise from my circuit polluting my 12V rail?

Reducing LED PWM Noise: Which is the best option?

LED + PWM EMC concerns

I need to investigate my setup a bit more, particularly the rise time of the MOSFET gate. 20 kHz doesn't seem too fast, but the edges might be the culprit. I also need to narrow down the issue to conducted or radiated EMI. Might even be an issue with my test setup, although that seems unlikely. I built the 20 kHz circuit on perfboard, but it's possible that the layout of my traces and ground path aren't optimal (I'm trying to fit this inside a very slim DIN rail case and there are challenges with packaging and placement).

I appreciate the response, Algoma!
 

Offline Algoma

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Re: PWM dimmers and supply line noise
« Reply #5 on: March 28, 2021, 02:41:53 pm »
Apologies, If figured you were driving the LEDs directly from PWM.  While you could put an lowpass filter outside the switching mosfet to smooth the DC, You want that pure PWM into its gate.

I've only got basic knowledge to share, but attempting to find solutions together is the best way to learn.

Both an RC and LC filter would soften the PWM signal. You want that mosfet to turn on and off fast without loosing efficacy during switching and overheat.

Perhaps a Mosfet driver, or gate drive transformer is the real solution to protect the gate from those spikes, overvolt those mosfet gates and and they can breakdown, an inductor in there could make it worse.
« Last Edit: March 28, 2021, 02:57:43 pm by Algoma »
 

Offline John B

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Re: PWM dimmers and supply line noise
« Reply #6 on: March 28, 2021, 07:41:56 pm »
Here's a handy way of visualising the current loops. I always filter the input current too as a matter of course. Component values are just rough examples.

Falstad link
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #7 on: March 28, 2021, 10:57:44 pm »
Here's a handy way of visualising the current loops. I always filter the input current too as a matter of course. Component values are just rough examples.

Cool idea! Thanks for posting the link with the current loop example. I'll have to try a few designs in the simulator and see what I can learn.

I've only got basic knowledge to share, but attempting to find solutions together is the best way to learn.

Totally agree! I'm happy to continue sharing what I find out as I debug this circuit.

I performed some further testing this afternoon. The PWM noise is making its way throughout the entire circuit. The 5 V rail is full of spikes, too. The EMI is also radiated, not just conducted--I can move my scope probe around the setup and pick up interference just by being in close proximity to the wires going to my LED load. Same story with the 24 V supply leads coming from the power supply.

The eBay circuit, while not the epitome of good design, also produces EMI and ripple on the 5 V rail. It's not quite as bad, though.

I also measured the rise time of the MOSFET gate signal. The eBay circuit is 25 µs, and my modified version is 1 µs. Probably a bit too fast in either case :). I'm going to play around with the gate resistor and see if I can soften the pulse, but hopefully not enough to cause overheating. I do have a few TC1428 gate driver ICs that I wanted to compare to the discrete BJT driver, so I can give those a try, too.
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #8 on: March 29, 2021, 02:40:39 am »
Scratch that last bit about the rise time... I was off by three orders of magnitude in my head :palm:. Rise times of microseconds shouldn't be an issue here, I don't think. However, stretching it to ~5 µs did make the noise pretty much disappear (at the expense of an ugly not-very-square wave).
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #9 on: April 02, 2021, 03:07:35 am »
I decided to start from the beginning and systematically check each circuit element to find and eliminate the noise. First up is the 555 timer running at ~12 kHz. The switching action produces a ton of noise on the 5 V supply rail. This rail is regulated by an L7805 and bypassed with the usual 330 nF and 100 nF caps on the input and output, respectively, plus another 10 µF on each side for good measure. The 555 is bypassed with 100 nF across its Vcc and GND pins.

The first attachment below shows the noise; upwards of 200 mV spikes. (I am triggering against the 555's output, but that waveform isn't used in the dimming circuit--the downstream comparator relies on the slope of the charging waveform.) I've used plenty of 555s in the past, but never bothered to examine the supply rails. I was surprised to see so much noise. This is a BJT-based NE555, so I presume that the CMOS variants are far cleaner.

To dampen the spikes, I put an LC input filter on the 555. I had exactly ONE suitable inductor in my parts bins--22 µH--but it was enough to test. Paired with a 100 nF cap, the voltage spike and associated ringing is greatly reduced. This filter produces a cutoff frequency around 100 kHz. Refer to the second attachment below.

I am pretty happy with the result. Next, I will examine the comparator. I expect to see some rapid switching at the threshold point. Might need to add hysteresis.
 

Online T3sl4co1l

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Re: PWM dimmers and supply line noise
« Reply #10 on: April 02, 2021, 09:52:43 am »
Put an R+C across the output transistor, source to drain.  Typical value say 10nF + 10R.

Note: the PNP is backwards.  The circuit works despite this, because the transistor isn't being overstressed, and has less (but not zero) hFE in this configuration (inverted operation).

Worth mentioning a 555 isn't needed, or a 393 isn't.  Two 555s or one 556 can be used to generate PWM, or a single 393 like so:



The same emitter follower and MOSFET output can be used, though at 10kHz the emitter follower really isn't very important, anyway.

Tim
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Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline gf

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Re: PWM dimmers and supply line noise
« Reply #11 on: April 02, 2021, 01:18:24 pm »
I wonder whether it is really a problem of the PWM circuit, or whether it is rather the 24V power supply which is unable to deal with the load transients resulting from this particular load. A PWM circuit is basically supposed to exactly that: Turning the load on and off. But the the 24V PSU may not be able to keep the voltage constant when the load current changes that fast, reacting even with overshoot.

Obviously a 100µF bypass capacitor suffices to catch the large spikes. Is residual ripple of ~200mVpp really a problem for you? Otherwise you'll need relatively large filter inductors and/or capacitors in order to reduce the ripple significantly. To get a rough feeling: The differential equation for an ideal capacitor is I=C*dV/dt. This means if you want to draw 1.3A from a capacitor for a duration of 90µs, and its voltage should not drop more than 20mV in this time interval, then you need capacitance of 5.85mF (note: milli, not µ!) - and its ESR would need to be very low either.

Btw, what kind of load is connected to the output of the PWM dimmer? Something like a LED strip (i.e. a couple of LED chips in series with a a current limiting resistor)?

 

Offline Algoma

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Re: PWM dimmers and supply line noise
« Reply #12 on: April 02, 2021, 02:29:11 pm »
Could always use a simple zeener diode to clamp those transient surges from getting into the PWM circuit / mosFET gate control.

If you can't stop them, block them, with a bit of surge protection.
 

Online TimNJ

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Re: PWM dimmers and supply line noise
« Reply #13 on: April 02, 2021, 02:40:30 pm »
What does the drain-source voltage of the main switching transistor look like? Usually a hard switched PWM circuit needs some sort of snubber to damp out the turn-off ringing.

30V rated MOSFET on a 24V rail? Hmm. If driving a load which is mostly resistive and slightly inductive, the spike can be quite large. Easily over 40V. On the other hand, I've also built a similar circuit to your 555 + 393 circuit above to drive some LED strips. I found the drain-source overshoot/ringing was not so bad. I didn't think about it too much, but maybe something to do with LED reverse recovery behavior. Not sure.

Most likely, the positive-going spike on your supply rail is due to the abrupt turn-off of the main MOSFET, and the negative-going spike is due to series inductance between the power adapter and LED strips. The turn-off spike is also related to the series inductance between the switch and the power source. By adding a 100uF local capacitor, near the PWM circuit, you reduce the inductance of the switching loop. Plus, you give the turn-off spike somewhere to go.

You can also simply play with the value of R7 to reduce the switching speed of the MOSFET. Higher value = slower turn-on/turn-off = smaller spike amplitude. If you have a way to monitor the temperature of the MOSFET, you may find that it's running quite cool as is. If you bump up the gate resistor to 470R or higher, you will incur more switching loss, but it may be acceptable. Also, the higher the switching frequency, the more switching loss, of course. There's not too much reason (that I can see) to operate an PWM LED dimmer at 10KHz+. On the other hand, 1KHz is close to the sweet spot for human hearing. If your SMPS is being asked to supply 1KHz load pulses, this may make some audible noise...but it really depends.

« Last Edit: April 02, 2021, 02:51:59 pm by TimNJ »
 

Offline Zero999

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Re: PWM dimmers and supply line noise
« Reply #14 on: April 02, 2021, 05:46:26 pm »
A filter on the power input is a good idea.

I don't think there's anything wrong with the PMW circuit, but it does seem crazy to use the 555 timer, a voltage regulator and the 393, when only the latter is needed. Here's a circuit which just uses the LM393.
« Last Edit: April 28, 2021, 10:06:02 am by Zero999 »
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #15 on: April 02, 2021, 11:13:32 pm »
Thank you for the help and suggestions everyone. The dimmable LEDs were supposed to be a quick upgrade to my bench, and then I went down the rabbit hole with switching frequency, voltage spikes, and circuit design. This is why I never finish any projects... I get too interested with the (sometimes irrelevant) details. :)

Anyway, let me see if I can address the various comments and feedback in the last few posts.

T3sl4co1l and TimNJ, thanks for the tip on the snubber. I've used these before on other circuits (mostly with BJTs) but didn't consider it for this one. I assumed that an input filter would be more effective, but I'll give it a shot. I still want to go through the circuit elements sequentially and see if I can eliminate as much noise as possible in each chunk, even just for my own interest and learning. Snubbing might be a solution on the MOSFET side.

gf, you raise an interesting point about the power supply and load transients. I've tried a few different supplies and they all experience the same type of spiking. The current rating of the supplies is about 2-3 times the load I'm drawing, so I presume they'd be able to handle the PWM surges at the lower currents. One of the supplies is an HP 6289A bench unit, which has 470 µF of output capacitance. Maybe that's not enough? As for the ripple being a problem, it's probably not--I just saw the spikes and figured it's not necessarily a "good thing." The LED driver is being run on its own supply, so it's not like it'll be interfering with other things on my bench. However, the radiated EMI could be a concern. I do see some background noise on my scope when the lights are turned on, so minimizing that would be helpful for general test and measurement purposes.

The load is a generic LED strip, cut to size: https://www.amazon.com/gp/product/B08MX6JKYQ/. This strand has about 200 LEDs on it. It draws about 30 W at full power (no PWM), but I've been testing at half that... PWM duty cycle ~50%.

Algoma, good thought on the zener approach. Something like this, perhaps? (Scroll down a bit.)

TimNJ, the eBay dimmer used an AOD472A MOSFET, which is only rated at 25 V! :palm: (Again, probably not the benchmark for good design, but I know what you mean.) Your description of the positive- and negative-going spikes is interesting. You mentioned series inductance between the power supply and the LED strip--do you think wire gauge could have anything to do with this? The run is about five feet and I'm using 22 AWG wire.

Earlier up in the post I mentioned about adjusting that MOSFET gate resistor. This actually made quite an improvement, but it completely distorted the input waveform. I think I had the rise time at upwards of 800 µs. I'll see if I can post a picture. I am not sure if the distorted gate waveform is an issue.

Tim, you're right about the switching frequency--the default 1.2 kHz caused a nasty resonance in the SMPS I'm using (it's even worse in the HP bench supply). I figured I'd try bumping that up by an order of magnitude, which then created problems with driving the MOSFET, which led to discovering the voltage spikes, and I'm back down that rabbit hole. If I end up driving these LEDs at high speed, I'll pick something above 20 kHz. My lab is very quiet and any sort of buzzing will be noticeable.

T3sl4co1l and Zero999, I will take a closer look at your LM393 circuits and see how they compare to the 555/LM393 arrangement I'm using. I like the simpler approach. I'm looking for user-adjustable dimming, not just a set PWM duty cycle. Zero's circuit seems to accommodate this, but in T3sl4co1l's schematic, would I just vary the voltage on the non-inverting input of IC1b to adjust the duty cycle? (I haven't spent any time really analyzing these circuits, so apologies for the novice question.)

More to come...
 

Online TimNJ

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Re: PWM dimmers and supply line noise
« Reply #16 on: April 03, 2021, 02:53:54 am »
Thank you for the help and suggestions everyone. The dimmable LEDs were supposed to be a quick upgrade to my bench, and then I went down the rabbit hole with switching frequency, voltage spikes, and circuit design. This is why I never finish any projects... I get too interested with the (sometimes irrelevant) details. :)

Anyway, let me see if I can address the various comments and feedback in the last few posts.

T3sl4co1l and TimNJ, thanks for the tip on the snubber. I've used these before on other circuits (mostly with BJTs) but didn't consider it for this one. I assumed that an input filter would be more effective, but I'll give it a shot. I still want to go through the circuit elements sequentially and see if I can eliminate as much noise as possible in each chunk, even just for my own interest and learning. Snubbing might be a solution on the MOSFET side.

TimNJ, the eBay dimmer used an AOD472A MOSFET, which is only rated at 25 V! :palm: (Again, probably not the benchmark for good design, but I know what you mean.) Your description of the positive- and negative-going spikes is interesting. You mentioned series inductance between the power supply and the LED strip--do you think wire gauge could have anything to do with this? The run is about five feet and I'm using 22 AWG wire.

Earlier up in the post I mentioned about adjusting that MOSFET gate resistor. This actually made quite an improvement, but it completely distorted the input waveform. I think I had the rise time at upwards of 800 µs. I'll see if I can post a picture. I am not sure if the distorted gate waveform is an issue.

Tim, you're right about the switching frequency--the default 1.2 kHz caused a nasty resonance in the SMPS I'm using (it's even worse in the HP bench supply). I figured I'd try bumping that up by an order of magnitude, which then created problems with driving the MOSFET, which led to discovering the voltage spikes, and I'm back down that rabbit hole. If I end up driving these LEDs at high speed, I'll pick something above 20 kHz. My lab is very quiet and any sort of buzzing will be noticeable.


By input filter you mean what? The root cause of the large positive going spikes is the MOSFET abruptly interrupting current in the main switching loop. The total loop inductance is the inductance of the load but also the series inductance between the power source and MOSFET switch. Long thin wires have higher inductance than short fat wires. When you put a capacitor of sufficient capacitance and low enough ESR local to the switch, you reduce the effect of the feed wire inductance. Now, most of the switching current is from the local capacitor. But so long as the load itself has some inductance, this can only help so much.

Remember V = L* (di/dt). So, the greater the inductance, the greater the voltage spike, and, faster the di/dt (i.e. faster the switching edge is) the greater the spike. Often times, “the load is what it is” so you just have to work with it.

What do you mean by the gate resistor distorted the input waveform? Input of what?

When you said the 1.2KHz board caused a nasty resonance, do you mean a mechanical “resonance“ causing audible noise? If so, this may be related to you demanding a square wave current with large excursion from your power supply. Square waves will make more nasty overtones than a sine wave. Think of how brash a square wave sounds on a synth compared to a sine wave.

You can smooth out the current from the power supply by putting an LC on the input of your dimmer. Maybe a few microhenries and a few hundred microfarads. The ‘C’ becomes the local capacitor above. Same concept as above except now you intentionally add inductance to prevent the dimmer from drawing square wave current directly from the power adapter. In this case, the capacitor will see a much higher value of RMS ripple current and needs appropriately high ripple current rating.

 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #17 on: April 03, 2021, 02:34:40 pm »
Ah, okay--I think I understand what you mean about inductance in the switching loop. Thank you for explaining it in more detail.

Yes, the audible noise was caused by a mechanical resonance at the 1.2 kHz PWM frequency. I see what you mean about the square waves producing the harsh sound--those waveforms do sound rather awful on a synth. For the discussion that follows, I've raised the PWM frequency to 21 kHz. I know the resonance might still be there, but it's not audible anymore.

By "input filter," I meant a filter on the 5 V and 24 V supply rails at the circuit. Earlier up in the thread, I mentioned that I had success with an LC filter on the 5 V rail to eliminate the voltage spikes caused by the 555 timer--this was just the timer, with no other downstream components. Here's a picture and some waveforms to clarify. Since this approach was effective in eliminating the spike from the 555, I thought a similar method would work on the 24 V rail. I think this is what you're getting at in your last paragraph above. (Edit: these plots include the MOSFET gate waveform, but that's just because I already had it set up on my bench that way. You can see the 555 spike overlaid with the ripple from the MOSFET switching.)



Regarding the gate resistor and waveform distortion, I was referring to the input of the MOSFET--poor choice of words; I should have said "PWM waveform from the LM393 output to the gate of the MOSFET." Here are two plots that show the waveform shapes and related thermals. With no gate resistance (R7 in my schematic from Post #1), the rise time is around 1 µs and the 5V rail exhibits sharp transitions and spikes. If I raise the gate resistance to 1k (4 µs rise), the edges are more gradual and the spikes disappear. The ripple is still there, but the peaks are gone. The second waveform is also not a nice square wave anymore; it has a "kink" on the rising and falling edges. Both waveforms also ring after the gate turns off. Note that the slower rise time also causes the MOSFET to run about 10 degrees F (6 degrees C) hotter, which makes sense.



I also checked a few other things, mostly just out of curiosity:

  • The BJT gate driver needs to have its base current limited to not produce a spike on the 5 V rail (R6, Post #1). I still want to compare the performance of this discrete solution with a dedicated gate driver chip.
  • Running the 555 at a lower frequency (500 Hz) doesn't really affect the supply rail ripple. The rise time of the PWM signal is the same, so I guess this makes sense (since MOSFET switching speed is related to the voltage spikes). The ripple shape is different, though. No difference in ripple or spikes at this frequency if I drive the MOSFET with the BJT driver or via the LM393 output directly.
  • I see ringing on the 555's timing capacitor when it transitions from discharging to charging (the valley on the triangle-ish wave). Not really an issue, but interesting. I wonder if it's due to the TTL architecture.
« Last Edit: April 03, 2021, 03:12:15 pm by iroc86 »
 
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Offline Terry Bites

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Re: PWM dimmers and supply line noise
« Reply #18 on: April 03, 2021, 04:41:50 pm »
Common mode choke and parallel caps
 

Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #19 on: April 20, 2021, 09:04:55 pm »
I found some time to get back on this project and decided to revamp my approach. I figured I'd post some results in case this thread is helpful to anyone else. FWIW, none of what I'm investigating is really "improving" the circuit; the ripple and noise seem to have no effect on its operation. This is turning into an educational pursuit. I have a question at the end for the experts, too.

Sticking with the 555+LM393 (for now), I rebuilt the circuit on perfboard to eliminate any parasitic effects from the original solderless breadboard version. I won't say that this improved the ripple and noise, but I feel more confident that what I'm measuring is actually reflecting reality. I also paid more attention my probing strategy to minimize ground loops.

Here's the new schematic with the important updates highlighted in yellow--mostly just adding capacitance. C1 and C4 are local to the 7805 regulator and removed a few peaks on the 5 V rail. The TTL NE555 continues to be a troublemaker, producing a nasty spike when the output switches. I added C6 across pins 1 and 8 to alleviate this, but I suppose it's the nature of the beast with this chip.





The biggest improvement came from placing C11 directly on the 24 V LED supply line and as close to the MOSFET as possible. The waveforms below show the ripple and noise on both the 5 V and 24 V rails measured at the 7805 regulator. Without C1 and C11, the 24 V rail has almost 2 Vpp of ripple! With the caps, this drops to less than 70 mVpp. The 5 V rail is not affected quite as much, probably due to the switching characteristics of the NE555 as noted above.



A few posts up, TimNJ had mentioned that my 30 V MOSFET was probably not the best choice for a 24 V rail due to overshoot during switching. When I put my circuit back together and connected up the LED strip, instead of my dummy power resistor load, Vds was reduced to just 10 V due to the voltage drops across the diodes. I think I'm good for this application, but I wanted to get some advice on snubbers and clamping.

As an experiment, I added an RC snubber via R9 and C10 using this calculator, which is based on an app note from NXP. In the waveform below, the snubber effectively reduces the ringing. It's immaterial for my purposes, but interesting nonetheless.

I am more interested in learning how to properly clamp the overshoot on Vds when the output state switches. My LED dimming circuit doesn't really sufffer from overshoot because I've selected a rather large value for R8, the gate resistor, to limit the switching speed and avoid noise on the supply rails. The 1k resistor produces a rise time of about 800 ns.

For the sake of argument, let's say that I wanted a faster edge but needed a way to address the Vds overshoot. The RC snubber isn't designed to do that, so would I clamp Vds instead? This app note from Semtech suggests putting a TVS between the drain and source, similar to how you might clamp the gate on a MOSFET. I can't really think of any drawbacks to this technique. Is this common practice, or are there other approaches?



« Last Edit: April 20, 2021, 09:06:37 pm by iroc86 »
 

Online T3sl4co1l

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Re: PWM dimmers and supply line noise
« Reply #20 on: April 21, 2021, 02:36:01 am »
Yes, TVS is a common approach.  Choose a rating higher than +V nominal max, and choose MOSFET Vds 20-30% higher than that rating (or >= the TVS Vpp).

Under this criteria: say nominal maximum is 28V, then you should be using a 28-36V TVS say, and a >50V MOSFET.  30V is cutting it too close, yes.

Can also use a peak clamp snubber, or dV/dt snubber.  This is a series diode, from drain, into an R||C.  For the peak clamp, R*C >> sqrt(L*C), so that the overshoot (which would otherwise be a segment of an LC ringdown waveform) gets clamped by the C (basically just another segment of an LC ringdown waveform -- the diode is connecting the C in parallel with the existing LC -- but a very much flatter one owing to the relatively large C, and hence having lower peak voltage, hence the value).  Inbetween pulses, the R discharges C to a convenient level; it might not be literally in parallel (i.e. to source or ground, which is where the capacitor should always be returned to), as that might draw DC current; it can return to +V instead, in which case the resistor bleeds off any voltage in excess of +V, and as long as the rep rate is low, the capacitor doesn't get charged up or anything and it does the job.

Or they can be the other way around, R||C to drain, diode to source/ground, though that doesn't work out so well when the R shouldn't be sapping (AC) load current.  This is more relevant with the...

dV/dt snubber: this works similarly, with different values.  Typically R and D are in parallel, and that goes in series with C.  This makes the C normally discharge towards whatever the drain voltage is (rather than to +V alone).  Note this puts the R+C on the drain, which means you can dimension it doubly for dV/dt snubbing and dampening.  For dV/dt, take the peak load current at turn-off, desired rise time, and rise voltage (+V more or less).  Put all these together and you get the capacitor value: C = I Δt / ΔV.  R can then be set to help dampen the drain node (when stray inductance is known), or at least to a maximum value determined by minimum pulse width (since the capacitor needs to be discharged (say 2 to 3 * RC) in the shortest on-time of the switch).

Note that a dV/dt snubber performs worse at low current, since ramp rate is proportional to load current.  So it's nice for just taking the edge off, giving the transistor a bit of a break during what is otherwise a hard switching event, without doing so much work that it greatly affects operation at either end of the spectrum.  Say you turn off the transistor in 20ns, and let it ramp up over 60ns; this saves a ton of switching loss from the transistor (mostly diverting it to a dumb resistor; for ramp rate comparable to switching speed, there is actually a minima in total losses however).  Meanwhile, it still goes an acceptable say 1200ns rise at 1/20th load current, lumpy but acceptable for a low-100s kHz converter.  And below that, you might have a pulse-skipping behavior anyway, which helps manage the relatively poor efficiency in this condition.  (More commonly used in SMPS than general purpose load switching.)

For schematic clarity, here's a combination RC damper and dV/dt snubber, in a flyback converter (with drain side current transformer):



The reason for both in this case was, the stray inductance of the dV/dt snubber itself, roughly 20nH, is still a lot, itself resonating with the transistor capacitance.  The 2.2R + 10n has somewhat lower inductance, so acts alright to dampen the node; but it can't be perfect, not with the axial components used.  (A few chip components in parallel, would be able to get inductance low enough for a good quiet "thud".)  You can see how lumpy it still is:



Also note the scale, this (snubbing) is going on over 200ns.  Peak load something like 10A I think it was?

Tim
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Offline iroc86

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Re: PWM dimmers and supply line noise
« Reply #21 on: April 25, 2021, 12:08:19 pm »
T3sl4co1l, I need to give you a really big "thanks" for such an informative and helpful reply :-+. The detail you provided helps me to better understand the use and purpose of TVS diodes and snubbers. The selection process you outlined is also great--oftentimes we see generic techniques without any real explanation as to why component values are selected or how to design for them. I'm not an EE or electronics designer, so learning from real-world applications is quite helpful. (To be honest, this thread has been really informative across the board. Thanks to everyone who's replied back with help and guidance.)

If you're willing to take the discussion a bit further, I'm curious about the use cases for snubbing, clamping, and edge rate tuning in the context of a MOSFET switching circuit. When should one solution be used over another?

Using my PWM dimmer as an example, this circuit doesn't really require a fast switching edge. By tuning the gate resistor, I pretty much eliminated the Vds spike to a reasonable level. The overshoot reached something like 70-80 V at 100 ns rise versus 30-40 V at 3-4 µs rise. (Just speaking in generalities; results based on testing with a load resistor, not the LED strip with the diode drops.) In this situation, one could probably argue that clamping/snubbing isn't really necessary. The MOSFET doesn't experience any undue thermal effects from the slower edge and the circuit performance seems okay.

When is the slower edge not an appropriate technique to lessen the overshoot? Is it still good practice to include a clamp or snubber even if voltage spikes aren't observed under normal test conditions?

Lastly: if we specifically consider ringing, how does one decide if the oscillations need to be addressed? By measuring EMI at the resonant frequency? In the second-to-last picture that I posted above, my PWM circuit had some ringing, which I mostly corrected with the RC snubber. Let's say this was a real product... how would a designer decide to include--or not to include--the snubber?

This is probably getting way into the weeds for a hobby circuit, but I like best practices. :)
 

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Re: PWM dimmers and supply line noise
« Reply #22 on: April 25, 2021, 04:19:33 pm »
You're welcome!


If you're willing to take the discussion a bit further, I'm curious about the use cases for snubbing, clamping, and edge rate tuning in the context of a MOSFET switching circuit. When should one solution be used over another?

Depends on range in load (current and impedance), energy dissipation required, efficiency, and all the other things like size, cost, EMI and so on.

No snubber at all, is usually acceptable for a tight layout with modern transistors.  Switching is reasonable to fast, and the extreme change in Coss with Vds provides a similar effect.  Layout must keep inductance low enough not to mind; which can be difficult when THT transistors are ~7nH a pop, plus routing.

7nH might not sound like much, but two of them back to back, with a bypass cap right beside them, is easily 20nH.  If Coss ~ 1nF, the resonant impedance is sqrt(20nH / 1nF) ~= 4.5 ohm, and frequency 1 / (2 pi sqrt(20nH * 1nF)) ~= 36MHz (1/4 wave in 7ns).  A risetime under 15ns will show peaking or ringing.  The ringing can be damped with an RC in parallel with each transistor (R ~ 4.5 ohm and C > 1nF), but the network has to have much less than 20nH to be effective, and it's already at a disadvantage being placed at the bottom of the 7nH lead length of each respective transistor.

To make that clear, in a half bridge inverter there are the following 1st order parasitics:



Q and D are the two switches; obviously a D has passive function, but all that matters is that one or the other (or both, or neither, as the case may be) goes between a reasonable open circuit, or short circuit.  "Reasonable" meaning, an impedance much much higher or lower than the surrounding impedances.

So, if the loop impedance (Ls + ESLin with Cq or Cd) is around 4.5 ohms, on resistance should be much lower than that, and off resistance much higher.  Which if these were say 600V 20A transistors/diode, figures like 100mohm and >>10Mohm would be typical, so, yeah.  ^-^


Ringing magnitude is determined by load.  At no load (Io = 0), the output voltage just sits around between switching events, and when one or the other device turns on, it starts at full Vin and pulls down to ~0 across itself.  This discharges its own capacitance (dissipating immediate switching loss), and shorts Vin across the remaining series resonant tank, (ESLin + Ls) + (Cq or Cd).

If we assume the device switches instantly, then the voltage across that inductance starts at Vin, swings to zero and reverses, and so on, ringing down.  Meanwhile, the current through the loop starts at zero, peaks at Vin / Zo (say for 400V and 4.5 ohms, 89A), then down, reverses and so on.

With no load and ideal components, only Rds(on) dissipates energy, which if Rds(on) = 0.1 ohm, the Q factor is (4.5) / (0.1) = 45, it'll ring like a bell.

In practice, Q or D probably doesn't switch quite as fast, and the amplitude will be somewhat lower.  Or, if your loop inductance is much higher than this, well, now you can see the problem!

Conversely, if load current is high at the instant of turn-off, Q's voltage drop starts at zero and its current starts at Io.  (We assume Io is constant during commutation -- typically, it is a much larger inductance than Ls and friends, and this will be the case.)  Cq charges, and Cd discharges, by Io.  Quickly, current starts to divert from Ls, into ground -- this change in current excites the series loop in the same way, and we get a peak voltage around Io * Zo.  Which if that was 20A and 4.5 ohms, is only 90V, not bad.

Which might look a lot like this, using exaggerated capacitance to show the effect:



Notice that commutation is so long that the load current is noticeably rounded off, rather than being a nice sharp triangle wave!  You can also see just a little blip of ringing at each turn-off event, as current is transferred from the respective switch, to the snubber capacitor.

The ripple at the top and bottom of the trapezoid, by the way, is that change in current propagating through the supply network.  The supply is not simply a capacitor with some ESL, but some ESR and maybe higher level structure as well, connected to other capacitors in turn, through wires (and in turn, inductances!).  This can make a complex network, even a lumped-equivalent transmission line -- and in the same way, we seek to dampen that network by putting some resistance on it.  Typically, a bulk capacitor with Cbulk > 3 * Cfast and ESR = Zo provides this.  Electrolytics are lossy capacitors: a curse and a blessing, they can be used to provide this function in addition to handling modest ripple currents (a few amperes for something of suitable rating in this example) and providing current inbetween mains cycles (mains filtering or PFC).


So, we can have a situation where ringing is worst at no load, and better under load.  Or maybe we have a converter with enough load inductance on it by default, that it sits in the ZVS regime (like the above waveform), but as load current increases, ringing also increases.  In general, there's a parabolic curve of losses, as you go from capacitive load (current lags voltage: when a transistor turns on, it "yanks" the load down), to resistive to inductive load (voltage lags current: when a transistor turns off, voltage swings across to the other side which "catches" it -- in a dual transistor half bridge, we use MOSFETs which have intrinsic body diodes, or IGBTs with co-pack diodes to provide this function).  Under a capacitive condition, hard turn-on switching occurs, and losses are driven by the voltage swing into the capacitances; under an inductive condition, hard turn-off switching occurs, and losses are driven by the current swing into the stray inductance.

It's a tradeoff; a good design balances both.  It can indeed be fruitful to intentionally increase Cq/Cd or Ls to achieve this -- mind, this will typically be done in combination with a snubber, to limit the consequential peak current or voltage.  This is always more true as time goes on.

Common advice is to simply "minimize inductance" and leave it at that, but I think that advice was written back in the days of slow BJTs and early MOSFETs: when you have 200ns+ to wait on the voltage or current changing direction, it doesn't much matter, you can get away with a lot.  (Most power supplies used single layer PCB back then... for that matter, they still do, too!)  Already in "old" history as electronics go (80s-90s), we had cheap and plentiful MOSFETs, fast enough to make one question that advice.  Since the 2010s, we've had them fast enough to handily violate that; and now that we have SiC and GaN MOSFETs widely available, with sub-ns switching times possible, it's utterly unavoidable! :D

To wrap up this line of thought: what you're really optimizing is, getting Zo to a modest fraction of Zsw (for Zsw = Vin / Io(max), say), so that Vpk and Ipk are only modestly above Vin and Io(max); and getting the 1/4 wave time shorter than the switching time.  If you can't meet these by adjusting Ls and Cq (through layout and component choice), then consider raising t_sw.  If you can't (because of efficiency spec, perhaps), next best is seeing if a damper (R+C) or snubber (RCD?) can do.  If not (because its own stray inductance is comparable?), you're really kind of stuck, and will have to adjust something else in the design (like not being so aggressive with the high switching frequency, or choosing a different device family (GaN over Si?) or topology (resonant over pulsed?)).


Oh, and to clarify this fact: inductance and capacitance are proportional to distance.  The physical constants μ_0 and ε_0 are in units of H or F per meter; when we calculate an inductor or capacitor, we use the cross sectional area divided by its path length (just as you'd determine the resistance of a cylindrical wire*).  Or if the cross section is already known, as for a transmission line, it reduces to a geometry factor, and we can find L and C quite easily by just multiplying the constants by the geometry factor and length.  (The inductance and capacitance per length is often given in cable datasheets, or we can calculate the geometry factor from Zo and velocity.)

*Mind, EM fields don't usually have such simple shapes, and we have to integrate over space to solve for the total.  We might express the result as an effective area A_e and an effective length l_e.  For magnetic paths mostly constrained within a permeable core, this is a useful method, and hence you find exactly these parameters in datasheets of cores.


So back to the snubber.  The earlier post mentions a flyback converter, which means Ls is effectively the leakage inductance (LL) of the transformer.  This can be sizable, so it depends.  I forget what the windup was in that example; probably the primary and secondary are interleaved a few times, keeping it fairly low?  (Transformers are just transmission lines in action, again: anywhere you have two wires side by side, you have some inductance and capacitance between them!  Note, this is between the windings themselves (or between wires in each winding, for that matter), independent of the core -- this is different from magnetizing inductance.)

The dV/dt rate snubber is a good choice here, as it improves the transistor efficiency somewhat, and the amount of energy it has to handle is modest (because of the low LL transformer design).  The load is highly variable (peak switch current proportional to load current, more or less), so some compromise may be necessary, and it will affect efficiency at light load (where very little energy is coming out of LL, but the RC is still charging and discharging the full, whatever energy C holds at Vpk).

If the transformer were leakier, the compromise for a dV/dt snubber would be too great: to keep peak voltage down, the ramp rate might be impractically low even at full or half load, let alone at light load -- where it might not ramp up at all, fully absorbing (snubbing) what should be real output voltage!  In other words, at low enough throttle, the peak output voltage doesn't even reach the desired level (say for a 12:12V converter, it might be below 12V peak, even at zero load current), because it's all being burned in the snubber.  So, we might prefer a peak clamp snubber in this case: it still has to dissipate the leakage energy, but at least some still gets to the load, and who knows, there's a glimmer of hope we could still do something with that energy (the clamp node is basically a DC boost supply, we could add an auxiliary converter and "stir" it back into the supply from whence it came.. if we didn't mind, you know, adding a whole-ass 'nother converter).

There are also quasi-resonant snubbers, which tend to exhibit higher peak currents or voltages, and have more limitations (they're harder to apply, and not as efficient as one would hope), but can be useful when everything lines up just right.


This is probably rather abstract just hearing me talk about it, and not even putting numbers to it -- but it's easy to see in a simulation; and a good exercise to set up, really -- in fact, one could spend weeks, or, years honestly, simulating various aspects of these networks to get an intuitive feel for them.  (I ran many simulations in the, hmm, 2008-2012 span or so, building my understanding in just this way.  It feels so natural now, it's easy for me to forget how long it's taken to get here!)


Oh, another thing about edge rate -- a side-effect of Coss(Vds) being so nonlinear, the dV/dt of a bare transistor can be very high indeed, and doesn't even track very well with gate resistance -- because Crss (Cdg) is so small in that range, Miller effect may not be the dominant limitation.  Indeed, for these types, the Miller plateau is mostly the first 10 or 20% of drain voltage swing.  Which, like I said before, the switching loss on these types can be relatively low, and this is the mechanism behind it: if most of the time spent dumping charge into/out of the gate is done at low Vds, then the power dissipation will be low as well.

So, when you actually want controlled edge rates, it may even help to add Cdg.  Be careful here: it shouldn't take much (10s, 100s pF?), and it should probably have a series resistor to prevent oscillation (say, >10 ohm).  (MOSFETs with low-ESR capacitors across pairs of terminals, tend to oscillate at 100s of MHz.  I've personally made some SPA07N60C3 oscillate ca. 400MHz by putting a protective zener diode (1N4742) between source and gate.  They don't have much gain or power up at those frequencies, but it's still more than enough to blot out nearby TVs!)

You can also consider whether to limit the rate of voltage, current or both.  Current is done by source degeneration: the classic common-emitter (or source, or..) amplifier puts a resistor between this terminal and ground, and this simply limits signal gain (transconductance).  Use an inductor, and gain drops off at high frequency.  We should probably use a damped inductor, so an R || L or ferrite bead is a good option.  Not that we'll be limiting the rate too too much: it would have to be a fairly large inductor to get microseconds of ramp time.  This is usually used to just "take the edge off", and that's good enough for emissions purposes -- particularly radiated emissions in the >= 30MHz range.

And you might again come to the same question: which is better, and how much?  Well, we've got a ratio of voltage and current, an impedance; so we might consider the load impedance and how that relates to our switch.  I don't know that I'd take it any further than putting in a few ferrite beads and R+Cs, honestly, but if you happen to need really clean switching, or specific waveform generation, it's certainly something to consider.

And it has been done, after a sort, in IC form:
https://www.analog.com/media/en/technical-documentation/data-sheets/1683fd.pdf
Here, they're using active circuitry instead of passive components, and probably some quite clever solutions at that to work around the fact that it's driving an, in general, completely unknown transistor -- but what's impressive is that they did it at all.  But hey, LT doesn't disappoint. :)


Quote
Using my PWM dimmer as an example, this circuit doesn't really require a fast switching edge. By tuning the gate resistor, I pretty much eliminated the Vds spike to a reasonable level. The overshoot reached something like 70-80 V at 100 ns rise versus 30-40 V at 3-4 µs rise. (Just speaking in generalities; results based on testing with a load resistor, not the LED strip with the diode drops.) In this situation, one could probably argue that clamping/snubbing isn't really necessary. The MOSFET doesn't experience any undue thermal effects from the slower edge and the circuit performance seems okay.

So, you'll see more spike with more cable length -- again, length is inductance.  I...did you mention length and I forgot already, or did you not mention?  Anyway, something like 0.6 uH/m is a good starting guess for cable, and that includes whatever length of the strip is, or Idunno, maybe half of it on average since (..if?) it's the paralleled-strings kind.


Quote
When is the slower edge not an appropriate technique to lessen the overshoot? Is it still good practice to include a clamp or snubber even if voltage spikes aren't observed under normal test conditions?

For an inductive load, switch current is constant (see above reasoning!) until the voltage ramp stops, and then current ramps down.  The product of both is a triangle: V*I with I constant and V ramping is one slope, V*I with V constant and I ramping is the other slope.  So, full switching time, times peak voltage times peak current, divided by 2, gives the switching energy.  (Area of a triangle is width * height / 2.)

For a resistive load, current and voltage ramp at the same time, so the power is a slope squared: a parabola.  The area of this happens to be the same factors, divided by 3 instead (hurray for calculus you can do in your head!...well, sort of).

Another way of putting it is this: you're driving the transistor slow enough that the load looks, at least somewhat resistive, maybe still a bit of a mix (still with a bit of peaking, but much less than full speed).  This suggests a time constant, t = L/R, which the switching should be similar to or slower than.  So, if you know R_L and Ls, you know t.

Anyway, switching energy first of all needs to be less than the one-shot energy dissipation of the device, of course.  If it's switching regularly, you need to add up enough of them to get the average power: simply multiply by switching frequency to get this.

So you have roughly:
Psw = t_sw * Vin * I_L * Fsw / (2 to 3)

This, plus conduction loss, gives total switch dissipation.

Your dimmer doesn't need to run too fast.  ~100Hz would be just adequate for static visual flicker, but you will definitely see it pulsating out of the corner of your eye, or when making head/eye movements -- I'm particularly irritated by those damn pulsing tail lights so many cars have, when driving at night: they briefly leave a streak of dots in my visual field, did no one stop to think maybe this was a terrible idea?! -- but a few kHz will be challenging to see even with rapid movements.

So, you can afford quite a bit of switching loss, and this isn't a bad way to handle it.  I would put on the TVS for protection, probably an RC anyway just to provide some damping (whether or not I'm exciting much oscillation -- still a good precaution for EMI, as even the fractional mV feeding through from the large gate resistor can be sensible on a radio), and that's about it.  Maybe current limiting/protection too, for higher reliability (accounts for possible shorted load or cross-wiring), depends on circumstances.


Quote
Lastly: if we specifically consider ringing, how does one decide if the oscillations need to be addressed? By measuring EMI at the resonant frequency? In the second-to-last picture that I posted above, my PWM circuit had some ringing, which I mostly corrected with the RC snubber. Let's say this was a real product... how would a designer decide to include--or not to include--the snubber?

This is probably getting way into the weeds for a hobby circuit, but I like best practices. :)

Heh, well -- the full monty is, put your setup inside the test chamber, set it up under typical operating conditions, and see how much it's giving off.  Radiation depends on magic lengths of wires (odd multiples of 1/4 or 1/2 wavelength), so, who knows; you could just get terribly [un]lucky and have a setup that doesn't radiate at switching harmonics!  More likely, there are bands, clusters of harmonics that radiate visibly (exceeding threshold levels, or otherwise).  You start probing the circuit to see what's related to these emissions, and bring it down.  An exact analysis is rarely necessary, and the root cause might be idiomatic.  (Many products pass after a handful of engineers and techs stuffed them full of ferrites, bypass caps, shields and so on.  Lab time is expensive, and it's whatever works in those days/weeks you're scheduled for!)

More particularly, it is often related to ringing oscillations.  In the example I started with, a loop resonance at 36MHz, would show up as a peak of some breadth around that frequency.  How broad, depends on what the switching waveform is; if it's stable and periodic, it'll be a cluster of harmonics filtered by that resonance, and whatever else is coupling it out of the circuit (say, some capacitance to the heatsink, then through power/ground wires?).  Maybe it'll have extra peaks, as the loop resonance is split* with the resonance of other bypass or EMI filtering caps; maybe it has other peaks or clusters, due to other resonances in the circuit (maybe the heatsink isn't perfectly grounded, and resonates around some other frequency range as well?).  It may look like a forest of harmonics, or if the signal is modulated (PWM varying with some variable load, or FM for spread spectrum, or a non-PWM control like quasi-resonant BCM, or fixed on-time) it may just kind of blur together on the display.

Oh uh, that'd be a spectrum analyzer display, by the way.

*If you couple two equal resonators together, the total frequency response is not simply the product of both; under light coupling, that's about right, but above a critical point, the peak splits into two peaks some distance apart.  Under very high coupling, say you have a 1:1 transformer with equal caps on both windings -- the equivalent circuit looks like two caps in series (one total equivalent), in series with the leakage inductance; this gives the upper resonance.  The lower resonance is the two caps acting in parallel (as you might intuit) with the magnetizing inductance.  This is a good example as we can vary the coupling of a transformer; when k ~ 1, LL << Lmag and the resonances are far apart.  When k ~ 0, the primary and secondary tanks act independently (and LL isn't a very meaningful quantity as it tends off to infinity in this limit).

This is easily seen (but probably not so easy to intuit in terms of a frequency response or spectrum!) in a demo with multiple pendulums hanging from a common bar, etc.  In the time domain, the transient response (i.e. starting everything at some initial offset, and letting them swing down) has energy coupling from one to the other, alternately; the waveform at any given resonator is a sine wave with a sine wave envelope (amplitude modulated).  Well, an AM wave has the carrier and two sidebands, and therein lies your answer: the ringdown waveform is two peaks at those sidebands.  (It's actually AM DSB-SC, i.e. the envelope is not just a magnitude, but signed as well, and the carrier is null.  If you look closely, when one pendulum stops, it actually reverses its relative timing, and as the envelope approaches zero, it approaches then grows quickly -- it's the zero crossing of the signed, sine wave envelope.)

So, add Fourier transform to the reading materials. :)

Back to the ringing; damping will bring down the levels of that 36MHz peak, but also broaden it; and it won't do anything about the loosely coupled resonances at other frequencies.  The only way to reduce those levels, is to reduce the energy at those frequencies in the first place, i.e. not switching so fast (reduce dV/dt and dI/dt), or reduce coupling (use a smaller transistor on the heatsink, or an on-board device instead of a chassis mounted one?), or increase shielding (better grounding, add actual shields?).

Or filtering, of course; some things are just inherently dirty, and are easier to clean up afterwards.  SMPS are something of a poster-child of this: a square(ish?) wave is required for high efficiency, and so are the harmonics.  Just put more shielding around it, and filter the signals going through those shields.

Automotive is the same way: you've got explosions going off inside the engine, what the hell are you going to do about it?  The engine block itself is heavy metal, sure, but there's still some clicking and sliding audible through it, and heavy acoustic pulsations through the intake and especially exhaust.  These have to be filtered, usually with some combination of tubing (acts as a series inductor) and accumulator (tank, chamber or resonator; acts as a shunt capacitor or resonant trap).  Which can, in turn, be loaded with absorbent materials (perhaps fiberglass batting, or also the catalytic converter and air filter act as series resistors) to dissipate more acoustic energy.  A lot of engineering goes into just the right resonances to tune for power (because of course the input and output matching networks affect engine efficiency; the whole thing is a mess of a self-excited oscillator, simple in principle, but so, so chaotic when considered in any kind of detail!) while keeping noise down for both passengers and pedestrians.

Or even heavy metal itself isn't a huge barrier, if the noise source is stiff enough (low mechanical impedance, shall we say).  A lot of cars have straight-cut gears in reverse, and the sound of those gears meshing (probably more particularly, the oil squirting around them) is what gives the distinct humming-whirring when backing up.  Some cars even had it in forward... rough times, they were...  Gears are mounted rigidly to the casing, which vibrates with them.  Only solution is to block those surfaces from radiating acoustic energy into the air -- sound deadening to absorb it at the source, or shielding to hold it inside.  (So, transmissions mostly use helical cut gears, and nearby body panels have acoustic matting to absorb vibration and road noise.  Which also deadens the panels themselves, so they don't resonate as much -- they still carry outside noise when struck, but it's more a dull 'thud' than a resonant gong.)

Or if you prefer a hybrid example: electric motors with a lot of cogging (fans are often good examples..) also give pulsating torque; torque is average forward, but it's just that it's varying at all, is enough to have some acceleration in whatever's attached, the frame and fan blades, or the housing of a power tool, etc.  Power tools, DC/universal motors are a big offender, not just because of their pulsating torque but also the very rapid clack-clack-clack of the brushes over the commutator, also sparking a little as they go.  Tiny vibrations when you just turn one in your hand, but up at 30,000 RPM, it doesn't take much displacement to fill a room with noise.

I probably shouldn't delve too deeply into mechanical analogs, anyway; MEs have it harder I think.  Whereas E&M is mostly 0-1 dimensional until very high frequencies (~GHz) where 3D fields take over, mechanics are almost inseparably 3D; and not only that, but solids undergo so many more modes of motion (each carried by a wave of a different velocity!).  We might write an EM field matrix, but they have to write a strain tensor!  But also to, er, sort of balance that out... I think most of them just don't care, and wing it most of the time? :P  When you're doing so much experimentally anyway, I guess it doesn't matter all that much.  (See, I can conceive of these models, easily enough -- but damned if I want to solve them, I'll gladly simulate E&M fields much simpler than that!)  You were born with all the instruments you need -- your hands and ears tell all, or a microphone or accelerometer if you need finer resolution or quantitative measurement.

By "0 dimensional", I mean you can draw an equivalent circuit -- a circuit, in the abstract, has no dimension; we don't need to know the speed of light, or any lengths or anything, every node simply exists at the same instant in time.  (The mechanical equivalent is a mass-spring diagram.)  A one-dimensional circuit would involve transmission lines (which have length, but not width).

Going back to circuit EMI -- we can hand-wavingly guess that, if we're measuring signals on the order of mV on the scope, or ~60dBuV on the spec, and those signals are going out on long wires -- we should probably be concerned.  From there, more or less... play it by ear, as the mechanical types do. :)

Tim
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Electronic design, from concept to prototype.
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Offline Electro Fan

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Re: PWM dimmers and supply line noise
« Reply #23 on: April 25, 2021, 04:54:08 pm »

Going back to circuit EMI -- we can hand-wavingly guess that, if we're measuring signals on the order of mV on the scope, or ~60dBuV on the spec, and those signals are going out on long wires -- we should probably be concerned.  From there, more or less... play it by ear, as the mechanical types do. :)

This is a pretty long, interesting, and detailed thread and I didn’t read it entirely but approximately what’s length of the longest power or signal carrying wire in the circuitry?  Any chance that with wires carrying various power levels and signals at various frequencies that unintentionally lots of antennas are being made?
 

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Re: PWM dimmers and supply line noise
« Reply #24 on: April 26, 2021, 02:18:25 am »
Yes, that's a good question. :)

Traces are small, and when surrounded by ground planes (laterally, but obviously especially true of buried stripline traces), couple weakly to space.  So you need quite high frequencies, and strong resonances or signals, to get much trouble going that way.  Coincidentally, high speed signals are typically low level (e.g. ECL or LVDS's <1V swing), and necessarily well matched (to control reflections -- a clean signal also has low SWR, and low SWR is weak or no resonance, by definition :) ).

Preferably, such circuits are inside shielded enclosures anyway, so that we only have to worry about what's leaving the shield -- conducted emissions.  Likewise for low frequencies, you need quite a loud offender to radiate much on something the size of a PCB, but wires can be arbitrary length, and so too their coupling to space.

Nice thing about wires and conducted emissions: we can fall back on a 0-dimensional model.  Where the wire exits the shield, consider that an RF port.  That is, assert the shield as ground, and carry that ground wherever you go (e.g. extend it with a coax cable).  With a suitable decoupling network, terminate the cable into a representative impedance (typically 50-150 ohms, depends), and tap off that termination to the receiver (or for susceptibility testing: to an amplifier).

In this way, we capture fully 100% of emitted signals, in all bands; we can't really know for sure, in general, whether those signals would actually be offensive in any possible arrangement; but the assumption of a controlled impedance termination at least gives us an average case -- it's not a great one, but it's at least plausible, and more importantly it gives us something to work from.

That is, if there's much radiation coupling from some random wiring network (say mains wiring, or wherever these whatever cables are placed), that radiation manifests as a resistance in circuit, which dampens resonances, reducing the impedance matching ratios of them.  If that random wiring acts like various kinds of wire antennas, it likely gives a modest Q factor (~10ish?), and so the matching range isn't going to be much beyond a similar factor away from typical feedpoint impedances (e.g., a resonant monopole fed with 50 ohms).  More extreme ratios can occur, but we might not count on them because they're rarer?

As an example, consider a low impedance source.  Say there's a ground loop near a grounded connector.  Like an SMPS with poor layout, beside a USB port.  The common mode emission from this, might couple quite strongly into a resonant stub -- the source impedance being low, it needs a series resonant circuit to match that impedance up towards the impedance of free space (377 ohms).  This could happen with a 1/4 wave resonant length cable, or a shorter one with something bulky (acts as a capacity hat) at the end, or a 1/2 wave with something grounded at the end.  Or you might have multiple of these at once -- superpositions are fine here too...

Well, if these cabling situations were in free space, we'd expect them to be very nominal impedances (50-100 ohms say), so that's fine.  What if they aren't free, though?  We might consider wiring in an industrial context, running along steel girders, or inside raceway or conduit.  Now we get a situation much like microstrip on a PCB, or coax.  The fact that it's enclosed, shielded, hidden from free space -- means radiation resistance has less of an effect.  The Q factor could perhaps be higher in these cases, matching better to our assumed low source impedance.

Note also what's going on in situations like this: where there are multiple wires running together (conduits, raceways, multiconductor cable, harnesses), there's significant coupling between wires.  Also in an industrial context, we might have contactors switching on and off, motors driven by VFDs (which might be completely unfiltered PWM output..), etc.  Lots of sparky buzzing noise.  In particular, sparking contacts with long wires to inductive loads, produce rapid fire bursts of short pulses -- EFT.  So this is exactly how that spreads out.

Anyway, that's a possible situation, and maybe we should be concerned about unlucky cases like that, where a very mismatched impedance happens to couple strongly, as uncommon as that may be.  Okay, well it's a low source impedance, so it's a low voltage, right?  Might we miss it?  If the impedance ratio is say 1:100 -- and that's a fairly serious ratio at say >30MHz, being a few ohms or even fractional ohms -- we expect a 1:10 voltage ratio.  So, big whoop, just turn down your threshold by -20dB, you likely have more than enough dynamic range on a typical setup to do this.  All the more reason to exceed threshold by a generous margin, right?

And we can easily defeat such situations, by adding resistance in series: ferrite beads.  Note that it's not enough to use pure inductance, or capacitance.  Those will always resonate with some unlucky load impedance, and you get the same problem.  But resistance, you can't fool.  It's always there, and it can't be matched out (aside from negative resistance, which, good luck with that!).

Which also gives you some idea what to do if you have similar concerns on board.  The power distribution network (PDN) often has low impedances and wide mismatches; resonances can happen, and an especially sharp resonance might go completely unnoticed, until a load happens to cycle in just the right pattern to excite that resonance, then corrupts or resets or crashes.  MCUs handling random data can do exactly this, and randomness being what it is, it might be hours, days or forever between events -- very tough to reproduce!  So, good practice to have enough damping in that network (which is made up of capacitors and the inductance of connecting traces at least, if not filter inductors as well).  Here, we don't want a hard termination, that would waste DC; we use a coupling capacitor to block DC while providing AC termination.  In other words, a big fat bulk cap with selected ESR.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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