Author Topic: Question about Characteristic Impedance of a Differential pair  (Read 852 times)

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Offline LoveLaikaTopic starter

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I'm working on a project using the PCA9615 IC to create a differential I2C bus. I'm having trouble with the differential trace pairs going from the IC to the resistor and the pins of the RJ-45 socket. You can see my example layout of one of the differential pairs in the image below (DSCL #7). This is part of a project where I'm trying to read from eight I2C sensors over a long distance, and using the PCA9615 IC seems to be the best way to do that. I've attached my schematic for one of the sensors and the current layout that I'm having trouble with.

According to the datasheet and the specs of a standard CAT 5e cable, my goal is to achieve a 100 ohm characteristic impedance. I'm using traces of 10 mils (0.254 mm in width) for the differential signal pairs.
The 0603-resistor pad spacing is 1.27 mm between the pads. conductor spacing is 1.016 mm between the traces. Plugging that into Saturn PCB, I'm getting 159.385 ohms. It gets better as I decrease the distance or increase the trace width, but I can only go up to 0.381 mm in width. Now, according to Section 7.2 of the datasheet:

Quote
The transmission line is terminated in the characteristic impedance of the cable, typically 100 ohms. This is the value defined by three resistors, the other two resistors providing the idle condition bias to the twisted pair

Since the resistors define the cable's characteristic impedance, is there a need to ensure that the characteristic impedance of the traces remain 100 ohms, or is that unnecessary? If so, how can I do so?
Datasheet Link: https://cdn.sparkfun.com/assets/a/5/1/3/6/PCA9615.pdf
 

Offline bob91343

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Re: Question about Characteristic Impedance of a Differential pair
« Reply #1 on: March 25, 2021, 05:16:45 pm »
Characteristic impedance is only important when the line length is more than, say, one tenth wavelength.  Further, an error of 10% represents an SWR of 1.1:1, not of much concern in most cases.  If you want to nit pick, and are using 150 Ohm line, you can add some resistance at the load to raise it to that value.  That way, with no reflected power, there will be no ill effects other than a slight reduction in received power.
 

Offline T3sl4co1l

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Re: Question about Characteristic Impedance of a Differential pair
« Reply #2 on: March 25, 2021, 05:37:03 pm »
It's I2C... hundreds of kHz...

Your PCB traces can be meters long in any orientation, and still not be noticed.  Don't sweat it.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline LoveLaikaTopic starter

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Re: Question about Characteristic Impedance of a Differential pair
« Reply #3 on: March 25, 2021, 05:42:05 pm »
It's I2C... hundreds of kHz...

Your PCB traces can be meters long in any orientation, and still not be noticed.  Don't sweat it.

Tim

Thanks for the reply, but though this is I2C, the PCA9615 converts it to a differential signal pair for each of the I2C lines. In that case, wouldn't we have to treat it as a differential pair?
 

Offline LoveLaikaTopic starter

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Re: Question about Characteristic Impedance of a Differential pair
« Reply #4 on: March 25, 2021, 05:55:44 pm »
Characteristic impedance is only important when the line length is more than, say, one tenth wavelength.  Further, an error of 10% represents an SWR of 1.1:1, not of much concern in most cases.  If you want to nit pick, and are using 150 Ohm line, you can add some resistance at the load to raise it to that value.  That way, with no reflected power, there will be no ill effects other than a slight reduction in received power.

Thanks for the reply. I see what you're saying. Assuming a standard I2C clock of 100 kHz, using C=3*108, wavelength would be 3000 meters, and 1/10th of that is 300 m. Since I'm only going as far as a fraction of that, <10 meters from IC to pins, impedance wouldn't matter. In that case, what are some best practices that I should incorporate? Would it be better to eliminate copper spots filled by the ground plane?
 

Offline T3sl4co1l

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Re: Question about Characteristic Impedance of a Differential pair
« Reply #5 on: March 25, 2021, 07:11:23 pm »
Thanks for the reply, but though this is I2C, the PCA9615 converts it to a differential signal pair for each of the I2C lines. In that case, wouldn't we have to treat it as a differential pair?

Yes, over such lengths as matter, or other circumstances.

If you had 3000m of CAT5, you'd need it to be differential and impedance-controlled, as indeed it is; over 10m, it's not too important, the impedance at least.

Although being a multi-master sort of bus, you can't use very long lengths anyway, that would screw up arbitration.  Bit times always need to be longer than the bus's electrical length.

And obviously, not like 3000m of CAT5 would carry the signal -- that's a lot of wire resistance!

What's more important, is keeping ambient noise out of the differential signal.  Noise tends to be common mode, for example they mention ground loop voltage in the datasheet.  This is rejected by the receiver (within its range), no problem.

Randomly routed wires would surely work for signal integrity purposes, but may pick up ambient noise as a differential signal.  This is what you actually need to avoid.  The impedance isn't very important, in DM or CM.  Just ensuring that noise is shared equally by both lines.



These devices are very similar to CANbus, though it lacks the common mode range.

Take note of Fig2-3 (page 4): https://www.nxp.com/docs/en/data-sheet/PCA9615.pdf
Drive is unipolar, and this is how they make I2C work, seamlessly, over a differential pair.  Instead of driving one line open-drain, two lines are driven open-drain and complementary.  So the common mode emissions are low.  The receiver is differential, so the common mode rejection is good, at least within the operating range.  Multiple devices can be attached to the line, and all will drive in the same direction, preserving the wired-OR arbitration mechanism that I2C is based on (and CAN as well).

Curiously, 7.2.2 (page 7) is in direct conflict with the 2nd-last paragraph page 10, and Vcm page 17.  And they do not give an absolute maximum / limiting value for the differential bus voltages.

In short: when is differential not differential?

When it's not differential anymore.

That is, when the assumption that V(+) - V(-) = Vdiff fails.

For Vcm outside of the given range, the input receiver can't read it anymore, or the ESD diodes clamp the signal.  Either way, data gets lost.

(RS-485 and CAN have an input range that exceeds the supply voltage, by using divider resistors to sense bus voltage -- this reduces signal gain, so the receiver needs to be more precisely balanced, but is also much more robust against common mode noise.)

Whether this is an issue, who knows.  It might be worth using a common mode choke, so that CM noise can be filtered out.  CMCs are perfectly acceptable here, because the impedance is well defined and stable (unlike some buses -- USB in particular).  Maybe additional ESD protection as well, seeing as the internal protection is only rated for 2kV.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


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