Author Topic: Question on OpAmp phase margin stability analysis using LTSpice  (Read 239 times)

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Offline Georgy.MoshkinTopic starter

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Question on OpAmp phase margin stability analysis using LTSpice
« on: December 23, 2024, 11:09:54 am »
I want to understand the output of open loop gain analysis using famous LTSpice tutorial video. What bothers me is this quote from another board:
Quote
You may ask how do I know that your simulation shows Phase Margin  - I know it's phase margin because it shows 180deg at DC (at DC there is no shift in phase)  - see below.
I did a quick test using NE5532 opamp, and I see a 180deg at DC. Therefore, the dashed phase curve is a phase margin (I think no).
This statement seems incorrect. For example, if I plot v(OUT)/v(fb), the phase at DC will be 0, which is correct for a resistor or short circuit and confirms that LTSpice did not perform any addition/subtraction of 180 degrees to the result. So, I conclude that LTSpice outputs raw phase of v(fb)/v(inm).

I performed all the steps from the tutorial video in the editor, and it is obvious (to me) that the dashed line shows raw phase difference for the waveforms at "fb" and "inm" nodes. And we are trying to avoid this phase getting close to 0 degrees while there is some gain left to produce unwanted self-amplification.

Btw, I have this NE5532-based schematic tested on a real PCB and unfortunately it starts to oscillate when something is attached to its input (through a 100nF capacitor). But the open loop phase plot suggests that it should be stable, as it never reaches 0 degrees close enough. I was hoped to see some phase close to the zero degrees in LTSpice, but the margin looks good to me. So, I guess it may be a layout problem and/or the gain is too high and reducing it may help.  Would be glad for any advice.
« Last Edit: December 23, 2024, 11:13:50 am by Georgy.Moshkin »
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Offline Kurets

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Re: Question on OpAmp phase margin stability analysis using LTSpice
« Reply #1 on: December 23, 2024, 12:03:15 pm »
First, the circuit cannot work as shown because you bias it to 0V while providing only +12 and 0V supplies. Consider if you apply +10mV to the input, it should be amplified by -470/3.6, about -100, so 10mV positive input should result in -1V (negative) output, which is not possible without a negative supply to the opamp. As such, your circuit will not work as a linear amplifier for any positive or AC coupled signal (negative input voltage would work, but opamps tend to perform poorly with inputs shorted to rail).

Second, when you add 100nF plus your source impedance which may be reactive due to long leads or similar, you will get a different phase response than with a pure short (in your simulation). There is also a difference between simulating with signal injected at the opamp input, which looks at stability of the amplifier itself, amd breaking the loop at the feedback resistor, which looks at stability of the feedback loop.

The reason why your simulation works may be due to unrealistic behaviour of the opamp model. These often contain voltage controlled voltage source, and other ideal spice elements, making them representative only when your surrounding circuit respects the operating limits of the chip.
 

Offline iMo

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Re: Question on OpAmp phase margin stability analysis using LTSpice
« Reply #2 on: December 23, 2024, 01:18:42 pm »
Your amplification is 14500x (the above schematics) - thus the construction may play a role as well (like a feedback from the output to the input) when the stuff oscillates..
Btw., how are your both IN+ biased (the schematics)?
« Last Edit: December 23, 2024, 01:23:41 pm by iMo »
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Offline Georgy.MoshkinTopic starter

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Re: Question on OpAmp phase margin stability analysis using LTSpice
« Reply #3 on: December 23, 2024, 01:38:50 pm »
I should have posted the full schematic earlier.... I use single 11v supply, inverting configuration,  IN+ are biased at 5.5v by resistive dividers. I had a new idea that the problem may be with the AMS1117 which provides 5v for the sensor, I used ceramic caps, and they are pretty small. Need to check it with a scope.

UPDATE: problem solved!
I've placed input/output traces of dual opamp too close. I also was able to reproduce the problem in LTSpice by connecting input to output with a 3pF capacitors. Reduced gain on both stages by 6dB and it's gone (attaching new transient simulation).
« Last Edit: December 24, 2024, 01:18:03 pm by Georgy.Moshkin »
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