Yeah - I've tried (first taking RW high and all other pins low):
- Write address, latch in via rising ALE, leave ALE high
- Write address, latch in via rising ALE, leave ALE high, take MUX high
- Write address, latch in via rising ALE, leave ALE high take DS high
- Write address, latch in via rising ALE, leave ALE high, take RW low
- Write address, latch in via rising ALE, take ALE low
- Write address, latch in via rising ALE, take ALE low, take MUX high
- Write address, latch in via rising ALE, take ALE low, take DS high
- Write address, latch in via rising ALE, take ALE low, take RW low
I've confirmed the address is being latched and decoded correctly by the '138, and I can even talk to subsystems on the board by removing the GALs and connecting the outputs via 10K resistors to pull-up / pull-down the subsystem enable lines manually.
It's just these GALs I can't figure out the behaviour of...