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Reset Pins on Counter IC
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eev_carl:
Hi,
I was wondering why there are two reset pins gated together on this IC. Wouldn't one reset pin be enough?
https://www.ti.com/lit/ds/symlink/sn54ls93.pdf
Thanks,
Carl
Gyro:
It enables you to tie them to the binary outputs to achieve different divide ratios (among other things).
kosine:
Pinout looks the same as the 74LS93, some explanation is given on this page:
http://electronicsclub.info/74series.htm
"The counter is in two sections: clockA-QA and clockB-QB-QC-QD. For normal use connect QA to clockB to link the two sections, and connect the external clock signal to clockA.
For normal operation at least one reset0 input should be low, making both high resets the counter to zero (0000, QA-QD low).
Counting to less than the maximum (9 or 15) can be achieved by connecting the appropriate output(s) to the two reset0 inputs. If only one reset input is required the two inputs can be connected together. For example: to count 0 to 8 connect QA (1) and QD (8) to the reset inputs."
eev_carl:
Thanks for the link. It seems like these move in tandem for the reset function. Why not just one pin to bring the signal low like in a 555?
Plugging Qb and Qd into the two resets turns the counter to a decade counter.
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