I'd make an effort to not break that ground fill under the chip. You have room on the circuit board to route the traces so you won't break that.
Maybe move the IC half an inch or so lower, towards the center of the board.
Also, I'd try to get all traces come out straight from pads and then curve, not how you have MISO, SCK, D2 and D3.
I'd try to have a thicker Vcc trace on the top and not go with VIA around those traces. I'd probably either use a jumper wire (or zero ohm resistor) or route the 4 data traces on the bottom of the board breaking the bigger ground fill for a short distance.
The capacitor at the top on Vcc and GND could be rotated counterclockwise 90 degrees so VCC pad would be above the GND pad of the ceramic cap, and the GND pad right above the GND pin of the chip
This way you may have room for those traces on the left and not have to go to the bottom layer to route them. You'd still have to make the connection between the Vcc pads (ceramic cap and header) but that could be a short thicker trace on the bottom, if you bring all the header traces closer together on the top