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RF Active probe input impedance

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bson:
The BF998 has different input capacitance on the two gates; looking at the NXP datasheet it states Cg1 = 2.1-2.5pF and Cg2 = 1.2pF.  Assuming 2.5pF, if you use both gates like in your schematic you get 3.7pF.  That's very high for a wideband probe, typically they sit at 1pF give or take a little.  You could use only G2; look for example at Fig 17 on p. 8, where G1 is used for AGC and G2 for signal input.  (https://www.nxp.com/docs/en/data-sheet/BF998.pdf)  1.2pF is more reasonable.

Wolfgang:
Did you see this one ?

https://electronicprojectsforfun.wordpress.com/rf-measurement-techniques/high-frequency-probes/

You can cur back on input capacitance using a 10:1 divider.

Nitrousoxide:

--- Quote from: bson on December 13, 2018, 09:35:24 pm ---The BF998 has different input capacitance on the two gates; looking at the NXP datasheet it states Cg1 = 2.1-2.5pF and Cg2 = 1.2pF.  Assuming 2.5pF, if you use both gates like in your schematic you get 3.7pF.  That's very high for a wideband probe, typically they sit at 1pF give or take a little.  You could use only G2; look for example at Fig 17 on p. 8, where G1 is used for AGC and G2 for signal input.  (https://www.nxp.com/docs/en/data-sheet/BF998.pdf)  1.2pF is more reasonable.

--- End quote ---

I dont get it? I have the circuit configured similarly as shown in figure 17. The only difference is that im using dual supply (hence no need for bias circuitry on the input) and I have Vagc implemented as a voltage divider. Isnt that just using G2 for the signal input? Since everything else would be RF ground (or close to) upon small signal analysis?

It then follows that the only relevant capacitance affecting the bottom mos is the Cgs of the top mos, which would always be there, no?


--- Quote from: Wolfgang on December 13, 2018, 10:50:17 pm ---Did you see this one ?

https://electronicprojectsforfun.wordpress.com/rf-measurement-techniques/high-frequency-probes/

You can cur back on input capacitance using a 10:1 divider.

--- End quote ---

Thanks for the article, will give it a thorough read. Looks interesting.

bson:

--- Quote from: Nitrousoxide on December 13, 2018, 11:14:05 pm ---I dont get it? I have the circuit configured similarly as shown in figure 17.

--- End quote ---
My bad, for some reason I got the impression you had your gates connected together, with the two resistors for bias between the supplies!  :palm:

What does your board look like?

Nitrousoxide:
Schematic:


Its a four layer board. I originally decided to attempt with a two layer. However, I just couldn't justify the elimination of the power planes. Thus the stackup from top to bottom:
- Signal. Controlled impedance traces to 50 ohms. Flood fill polygon is grounded with via stitch.
- +5V
- -5V
- GND with via stitch.

I have removed all planes over/under most of the high impedance section. The rest is flood filled to act as coplanar waveguide.

Top:

Bottom:


Component values may be tweaked, some points will be 0 ohm jumpers too.

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