I was looking at some internal data transfer today on some equipment that is loading a register(s) and I see what looks like both rising edge keying and falling edge keying. For example, on one line, there is a clean clock running at about 4MHz. On other lines, there is data. At some times, the data is at the rising clock edge. (meaning all of the data values at the clock falling edges are zero. The data pin transitions between each clock cycle) At other times, the data is on a falling clock edge. Sometimes, the data appears mixed on the same line. (A packet of rising and a packet of falling on the same line.) Is this a standard protocol and if so, what is it called?