| Electronics > Beginners |
| Rising and falling edge clocked data transfer |
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| mriPaul:
I was looking at some internal data transfer today on some equipment that is loading a register(s) and I see what looks like both rising edge keying and falling edge keying. For example, on one line, there is a clean clock running at about 4MHz. On other lines, there is data. At some times, the data is at the rising clock edge. (meaning all of the data values at the clock falling edges are zero. The data pin transitions between each clock cycle) At other times, the data is on a falling clock edge. Sometimes, the data appears mixed on the same line. (A packet of rising and a packet of falling on the same line.) Is this a standard protocol and if so, what is it called? |
| MosherIV:
Hi. There is a standard serial bus called SPI. It does allow for data to be on rising edge or falling edge. |
| mriPaul:
I think the answer is as close as my RAM. It looks like a process called Double Data Rate (DDR). |
| helius:
Without knowing the setup and hold specifications for the data and control lines you are shooting in the dark. Some lines may be sampled at the rising clock edge, which requires them to be driven at the falling edge. Others may have different timing requirements depending on other context, for example, writes are different from reads. This is all a far cry from double data rate. |
| ejeffrey:
Some scope captures would be helpful to illustrate what you are talking about. Generally DDR transfers data on both rising and falling edges to double the data rate for the same clock. It sounds like in your case each transaction is either on the rising or falling edge not both, which is not what you expect from DDR. It would also be a bit unusual to have a DDR interface at 4 MHz, although that can happen if you have an interface designed for much higher speed but run slower in this instance. SPI can operate on either edge but only uses one at a time. It is theoretically possible to have a bus with multiple slaves using different clock phases, and have the master switch for each transfer but I have to say that would be extremely unusual. |
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