Rising and Falling EDGE detector

[Houseman]

Hi. For a school project I need to make in CMOS using simple logic gates / Schmitt Triggers a special circuit.
It seems terribly simple but it goes beyond my resources, so maybe with a little help from my friends..
There is as input a 1 Second Counter clock 0 5V
And a 120 second periodic square wave 0-5V
The output has to be active high (5V) only for the first 7+7 seconds of each edge transition of the 120 sec square wave and low for the other 53+53 seconds, twice for a period.
Attached is a simple diagram.
Can I get please some hints?
I know I use a S-R Flip-Flop to enable the output but I cannot find the edge detection circuit for both transitions.
Any help is greatly appreciated even if too simple...
Regards
Steve

[MK14]

Here are some clues.

https://electronics.stackexchange.com/questions/263889/edge-triggering-on-simple-logic

EDIT: Actually ignore that, I misunderstood the question.

Are you looking for a binary divider (Flip flop), type of solution ?

Hint2: Exclusive Or gates, might handle BOTH edges ?      

[Houseman]

Nope.
Already saw that.
But I need the same circuit to detect both rising and falling edge.
These detect just one type of them.
Rgards

[Houseman]

Ah, ok.
The types are indifferent.
I need just a working solution.
I cannot go beyond the edge triggering detection. I get one pulse on either falling or rising,
Thanks for the reply

[MK14]

Nope.
Already saw that.
But I need the same circuit to detect both rising and falling edge.
These detect just one type of them.
Rgards

As it is related to study, I need to leave you to figure it out yourself.

But I can assure, you that it can handle both edges, if you can work out the trick.

[MK14]

Ah, ok.
The types are indifferent.
I need just a working solution.
I cannot go beyond the edge triggering detection. I get one pulse on either falling or rising,
Thanks for the reply

>>I need just a working solution.

Surely you should be doing it, to learn from the exercise ?

I.e. Someone asks, will you do my homework for me, my answer is, "Sorry, I can't do that, no".

>>The types are indifferent.
I'm not sure what you mean ?

Is the solution, suppose to be all digital, e.g. A binary counter plus some gates ?

Or would an RC timing (analogue) type of solution, be acceptable ?

[Houseman]

Hi.Thanks MK14 for the reply.
Never thought someone way doing homework for me.
I agree with you. We must learn.
Solution all digital, if possible. It is part of a complete digital project.
RC timing also acceptable, yes, what do you mean?

The fact is that if I use the XOR with R and C on B input I get different timings on the output during the falling edge (longer).
I need same timing for both transition.
Thank You

[MK14]

Some hints to think about.

How many clock cycles, would a 6 stage (bit), binary (Flip Flop) divider take to count and wrap around ?

Can it be made to count to 60, for a 60 seconds per minute ?

During the first 7 seconds of such a count, is there any detectable pattern on the outputs, which could be used with some gates, to make the signals you want to create ?

[Houseman]

MK14 Thank You for the time and patience.

So I got the first part. using two inverter on input B that is tied to input A instead of the RC circuit I get same transition timing.

[MK14]

MK14 Thank You for the time and patience.

So I got the first part. using two inverter on input B that is tied to input A instead of the RC circuit I get same transition timing.

I'd not understood the required solution properly. Now that I understand it better, the RC circuit, is not the type of answer they are looking for. It would have done it, but is not properly digital, and is a bit inaccurate (e.g. 5% error in timings).

I think they want some kind of binary counter (divider) circuit, to solve it. Using Flip-Flops (I.e. binary counters), and gates to control them.

Like this:
http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/bincount.html

[free_electron]

use the CLK as a 'reset' signal for the flipflops
then send the other signal into the CLK of the flipflop ( one inverted, one not. )
and OR on the output and bob's your uncle. Whenever there is an edge you will get a 1 for exactly one clock period. use that to fir off another counter that times.

[eblc1388]

There is as input a 1 Second Counter clock 0 5V
And a 120 second periodic square wave 0-5V
The output has to be active high (5V) only for the first 7+7 seconds of each edge transition of the 120 sec square wave and low for the other 53+53 seconds, twice for a period.
Attached is a simple diagram.

Diagram timing don't match with description. The 6 or 7 second timing is critical as the possible solution will differ.

Assuming the diagram is correct, with the high timing to be 6 seconds, then you can obtain the desired output in the following way.

a. divide the input 1 per second clock by 6
b. fit the divided clock into a CD4017 so one of its 10 output goes high every 6 second and low for 54 seconds.  The cycle will repeat every 60 seconds.

If ON timing is 7 second, then in step (b) you will need to trigger a 7-second duration monostable using the 4017 output. The cycle will repeat every 60 seconds.
 

[MK14]

Diagram timing don't match with description. The 6 or 7 second timing is critical as the possible solution will differ.

Assuming the diagram is correct, with the high timing to be 6 seconds, then you can obtain the desired output in the following way.

a. divide the input 1 per second clock by 6
b. fit the divided clock into a CD4017 so one of its 10 output goes high every 6 second and low for 54 seconds.  The cycle will repeat every 60 seconds.

If ON timing is 7 second, then in step (b) you will need to trigger a 7-second duration monostable using the 4017 output. The cycle will repeat every 60 seconds.

It seems you also need to synchronise with the IN1 (120 sec period) signal. It is not 100% clear, if that is the case.

There are ways of achieving that. Such as using the low to high transition of IN1, to generate an extremely brief reset signal, into your counter(s). May need a slight extra delay, to avoid logic race hazards.

[eblc1388]

It seems you also need to synchronise with the IN1 (120 sec period) signal. It is not 100% clear, if that is the case.

Yes, true.

Another way of doing it would be to set up a monostable to trigger on both edges of the IN1(120 second period) signal, with a timing of 6 or 7 seconds.

[MK14]

It seems you also need to synchronise with the IN1 (120 sec period) signal. It is not 100% clear, if that is the case.

Yes, true.

Any way of doing it would be to set up a monostable to trigger on both edges of the IN1(120 second period) signal, with a timing of 6 or 7 seconds.

That type of solution was what I originally suggested (but using gates + RC's etc). But, the problem specification, might (the OP has not been 100% clear on the specification), need to be digital, and hence almost 100% correct timing.
Rather than the 1% .. 10% timing error (RC tolerance dependant), you would get.

The thing is, the OP, has been taught to use certain techniques and stuff. It is probably those that the 'Professor'/Teacher, wants the solution to consist of. Since we weren't on the course, that makes it harder for us.

I.e. The specification is missing, many possibly important details.

[Ian.M]

If the solution has to be entirely timed from the 1Hz clock (even if a fully synchronous solution is not required), there's also the issue of the phase of the 120 sec squarewave relative to the 1Hz clock. 

Does the 120 sec clock edge lead or lag the nearest 1Hz clock edge in any second it has a transition?

Different solutions may be required for either case.  Resynchronising the 120 sec squarewave to the clock is probably not an option as that could result in an up to one second delay.  Detecting lead or lag and dynamically selecting the correct delay would be possible, but slightly trickier than I would expect the instructor expects for a school project.

I've been playing with the problem in LTspice A device logic.   So far, it looks like a likely lineup is a XOR edge detector, setting a SR flipflop for the output, and resetting a Johnson ring counter.   The counter is decoded to generate a reset for the SR flipflop to terminate the output pulse after the desired delay.

Why a Johnson ring counter? Well, a synchronous counter makes it easier to avoid decode glitches, LTspice doesn't have a native JK flipflop A device, and implementing binary synchronous counters  with D flipflops is a PITA, as you want T flipflops which for a D flipflop based implementation, each need a 2:1 Mux to select between Q and /Q for the feedback.

[Ian.M]

I've had a brainwave - stretching the 120s squarewave detected edge pulse till the next 1Hz clock falling edge eliminates the race condition between the detected edge pulse and the clock rising edge.  Instead of a hairy RC or gate delay edge detector, for the XOR's delayed input simply pass the 120s squarewave through a D flipflop clocked on the 1Hz falling edge.

Sim results look good.

A minimalist practical implementation could be done in three chips: a dual D  type flipflop, a quad XOR and a 4017 decoded decade counter.  One D flipflop + two XORs (one to invert the flipflop clock) implement the edge detector.  The 4017 provides the delay (selectable from 1 to 9 seconds), and the other D flipflop is used as the SR latch for the output pulse.  If you are using a D flipflop with active low set and clear inputs, use the spare XOR gates to invert them.

Edit: Its now over 24H later, so I'm posting my sims.  There are two in the zipfile, one runs under LTspice, and has a .plt file attached for organised logic analyser style waveform display.  It uses the default LTspice 1V digital levels but should be pretty accurate in the time domain.  The other is built of 4000 series CMOS logic, and runs under a *very* old simulator: Microcode Engineering's CircuitMaker 6 Student (or Pro) in digital mode, and due to the limitations of its digital simulation has grossly exaggerated propagation delays. (I scaled it as 10 'ticks' per second and the minimum propagation delay is one tick).   The CircuitMaker 6 Student installer is called cmstudnt.exe and can still be found on the WWW at various reputable (.edu) sites. 

@Houseman,
Please try to resist the temptation to look at my solutions before completing your own.  If you are still stuck, show us what you've got so far and ask about whatever issues you have left

[RJSV]

  Here is my approach, and IC use:
 
  Textbook example, it is very fast, and so avoid (those) analog parts, at least directly into IC.  Please try look up the CD-4020, that's a good long interval.
  I noticed a lot of emphasis, on direct results: "... Such and such, Simulator didn't look good, or SPICE failed..."

  Good to run and evaluate, don't  take it bad. Just maybe more, slow detail. Here is an example: "I say a circuit for 300 hz square wave. It looks backwards, wasn't that a 'pull-up' circuit ?
  That is a maybe, partially navigating as you learn.
  Once you go all digital, try the classic:
 
   Rising Edge, to short pulse out:
   Place input to NAND IC gate.
   Take also into an inverter, just use another NAND.
    Run inverter into NAND, other input.
    That will spit, briefly, (downward), when the
     occasional edge happens.
     You got one part... So...
      By the way, I always try to put a bit more delay, just   
       just string into pairs of gates, to extend the pulse
      time.
      Thanks