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saleae logic ??

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--- Quote from: thakidd on November 22, 2010, 01:32:08 pm ---The question is...How might the OBLS be modified to have more depth?

--- End quote ---
FPGA with more RAM or external RAM. A second revision with external RAM was planned, but I don't know if it will materialize. There's a reason why many FPGA-based logic analyzers have these kind of limits.

OBLS is based on Sump LA (or in principle sump LA with PIC for communication).
I have two private versions of sump LA design based Logic Analyzers, both based on Altera Stratix :
- EP1S10 - with huge memory per channel and 64 chans
- EP1S80 - with fast clock/sample rate but only 64k per channel - which is even more than Intronix LogicPort.
So you can see there is enough room in sump LA design for improvements, it is only question about price
(the Spartan 3E used in OBLS is 440x cheaper than Stratix EP1S80)

There is another one free LA design available, miniLA:


I did some tweaks in VHDL and my buddy MockUp did some circuit improvements,
now we have 32 chans with 512k sample memory per channel, 100MHz sample clock, USB isolator (ADUM4160)
and of course USB powered (with some brand new DC/DC converters from Murrata).


Of course it costs more than OBLS (actually we have ~5 left, price about 160USD), but as always - you get what you paid for.

And btw, i have Saleae too, i do support people like Joe. For protocol sniffinig (like unknown displays), reverse engineering it is just perfect,
you can't have too much sample memory .. never.


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