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| Shift Register Problems |
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| gigavolt:
I think I have another clue to this problem I was able to catch one of the "double clocking" events in action using my oscilloscope. Ch1 is clock and Ch2-3 are outputs 1 and 2. I'm probing the clock line right on top of the shift register using one of those rigid ground leads right on the end of the probe. It looks like the clock line is ringing a ton and it felt like the double clocking events were more rare when I had the oscilloscope probe connected. Do you guys think that this could be the problem? Any recommendations on fixing it? @StillTrying, the 74HC164 is decoupled the same as the 555 with a 0.1uF right on top of it. I also added a 1uF ceramic just in case, but saw now change. |
| gigavolt:
Fixed it! I added ~100pF to the clock inputs of the shift registers and I don't see double clocking anymore. I'm guessing that this is due to the inductance of the wires I'm using to connect the two chips along with the capacitance of the breadboard conspiring to create some weird filter. I'm planning to put the design on a PCB in the future. Do you guys think I need to add the capacitors there as well? |
| StillTrying:
"I'm guessing that this is due to the inductance of the wires I'm using to connect the two chips along with the capacitance of the breadboard conspiring to create some weird filter." Yes, it looks like the fast 10ns falling edges of the outputs are getting back into the rising clock edge, and the 74HC164's GND might be rising as well. Breadboards, chip carriers and long wires are not the place for fast edges. :) If the 555 output is only clocking the 74HC164's CLK the faster switching of a CMOS TC555 might be better, it should pass through the logic 1 mid-level to towards V+ at least 5 times faster. The rounded droop on the CLK is strange. "I'm planning to put the design on a PCB in the future. Do you guys think I need to add the capacitors there as well?" With lower impedance GNDs and a lower impedance CLK you shouldn't have to load the CLK with a cap. |
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