Make sure you don't get into thinking that signal travels down one line and back the other. Each trace of a pair induces an opposite direction current on the closest conductor it can. This should be a plane, rather than the other pair. This is important to consider, because if you need to cross, you need to switch layers. Make sure that you have a method for the current that will be induced on the plane to continue. The absolute best situation is that you run the layer change from one side of the plane to the other. The distance between the conductors and layers will be different with most stack ups, so you will have an impedance change, unless you alter the trace width to compensate. If you have to jump more layers, make sure to provide a via path for the ground plane (with capacitive coupling if the induced plane is also not ground.)
Yeah, the coupling between edge-coupled differential is marginal at best, like 20-50%. Imagine the impedance between each line and to ground, the equivalent impedances act like a triangle with roughly equal values (like 150 ohms or so). So you get your 100 ohms differential, but there's still a whole lot to ground.
You can run differential traces independently, without worrying about the coupled distance. And you should, in that you should be aware that uncoupled lengths don't really matter at all. Crosstalk from unrelated traces is a bigger concern.
As for crossing, ideally, every time a high speed trace passes over a plane split (in a multilayer board, e.g., entering a different VCC domain) or through vias to the other side, that crossing should be accompanied by a bypass cap across the split or between layers, as near to the signal via(s) as possible. (And yes, that means a bypass cap from VCC1 to VCC2 -- you can do each one to ground, but you get a longer loop.) In practice, the effect is so marginal that it's nearly undetectable in TDR, because the plane-to-plane coupling is way better than the trace-to-plane coupling.
Differential has an advantage here, because as long as the signals are time delay matched, the up and down transitions cross the underlying discontinuity in an 'equal and opposite' fashion, so there is very little coupling indeed.
And to be perfectly clear, I mean a gap between planes on a given layer (perhaps between 3.3V and 2.5V supplies between different areas), with contiguous plane (ground?) on another layer 'supporting' that transition. Not a complete gap through all layers, which is generally a Bad Idea.
I'm also assuming that the split occurs in the layer nearest the signal traces; in a 4-layer board, you might have a completely solid ground but gaps in VCC, so one routing layer (top or bottom) will encounter a situation like this. With many layers, you might have the luxury of a plane for each, and not need gaps at all.
Tim
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