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| Simulate MC34063 on LTspice |
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| odgonza:
Hi. I'm trying to simulate the MC34063A. As you can think, that model is not available in the LTspice. I found one model from ON Semiconductors web for SPICE, and I had imported it into LTspice, but I have some problems. LTspice is a Linear Technology version of SPICE and can't use directly the simulation model I got from On Semi. The error that LTspice reports are: SPICE error log: Line 31 --> Error: unknown token in: "[~](v(9)&v(8))" Line 36 --> Error: unknown token in: "[~](v(4)&v(10))" Line 48? --> Fatal Error: Bad <cond> ? <true> : <false> syntax. A lot of years ago I studied PSPICE, but I can't remember the sintax now. I don't remember to use the symbol "~" (ASCII 126) in a SPICE file. Can someone give me an idea about how to solve my problem? |
| tinhead:
take this one, comes from http://tech.groups.yahoo.com/group/LTspice/ and sems to work |
| odgonza:
Great! It works! Thank you very much :-) |
| iMo:
Be aware the ltspice "models" are "models only". 100% deviation from the reality could be easily the case. |
| Ian.M:
The OnSemi MC34063 model you posted appears to be written for IsSpice4. See http://www.intusoft.com/lit/IsSpice4.pdf for the user manual. The line: --- Code: ---B5 5 0 V=~(v(9)&v(8)) --- End code --- is a IsSpice specific digital behavioural source, consisting of a NAND function - see page 176 (PDF page 186) of the user manual. For LTspice, you could try simply replacing the ~ with ! but the thresholds wont be correct, so it may be preferable to rewrite the line replacing the B source with a LTspice A (special function) AND/NAND gate, with instance parameters: --- Code: ---Vhigh=3.5, Vlow=0.3, ref=1.5 --- End code --- to match the IsSpice default behaviour. The easiest way to get the syntax correct is to place the A AND/NAND gate (lib\sym\Digital\and.asy) on a 'scratch' schematic, label its used pins with the model's numeric net names, and set its instance parameters, then View the SPICE Netlist to get a line that should be a 'drop in' replacement in the model: --- Code: ---A1 0 9 0 8 0 5 0 0 AND Vhigh=3.5, Vlow=0.3, ref=1.5 --- End code --- For lines like: --- Code: ---B4 6 0 V=v(2,90) > (v(vref,90) + v(voff,90)) ? 0 : v(vdd) --- End code --- the IsSpice ternary (If-Then-Else) operator condition ? true_val : false_val (see PDF page 189) can be directly translated to a LTspice if function: if(condition, true_val, false_val) giving: --- Code: ---B4 6 0 V=if(v(2,90) >(v(vref,90)+v(voff,90)) , 0 , v(vdd)) --- End code --- It may well be worth drawing up a schematic for the model in LTspice one line at a time, checking the netlist after each one to create a subcircuit of the model to aid debugging it. If you add the circuit elements in the same sequence as the lines of the model, the component lines in the netlist will be in the same order. Unfortunately comments and .model statements will be moved to the end of the netlist irrespective of the entry order. |
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