Low ripple low noise small power supply design

[VEGETA]

I think everything is perfect now. link in PM.

As for the mosfet, you are correct. it is due to op-amp. here are the 2 that we resulted into:

https://lcsc.com/product-detail/MOSFET_International-Rectifier_IRLR8726TRPBF_International-Rectifier-IR-IRLR8726TRPBF_C81137.html
https://lcsc.com/product-detail/MOSFET_KIA-Semicon-Tech-KIA50N03AD_C112249.html

I like the 2nd one due to huge availability and very low price. I think I will go for it unless a cheaper suitable one is available.

[BrianHG]

The KIA mosfet doesn't have any charts showing the Vgs curve.

Try this one : https://lcsc.com/product-detail/MOSFET_KIA-Semicon-Tech-KND3403A_C382143.html

Or you can trust the one you picked or find a data sheet with the Vgs curve table shown.

[BrianHG]

More errors.  Bad paste-mask for the switcher's footprint.

See the red arrows, the yellow pads are the openings on the paste mask to apply solder.  You have the paste on the heat-sink portion of the footprint instead of under the IC where it can bond with the IC.

Double check the footprint recommendations including paste-mask-opening and make sure you match them.

The green arrow is correct.

[VEGETA]

you mean the full pad should be exposed? I thought this was the case within the footprint itself...

looks like the part under the IC is not exposed while the one outside is... I think they both should be exposed so i can solder them manually if I want to. this is very easy to fix though, just modify the footprint.

What about the ones under the mosfets? should this be a little bit exposed so I can manually solder them since this is what I will do?

is there anything else besides this? so I can do them all together THEN panelize the board again.

[BrianHG]

What you see is not the exposed pad.  It is the SMT Paste stencil cut-out opening.  This is a large lazer cut metal sheet which JLPCB uses with a squeegee to apply solder-paste (like a silkscreen process) before the components are mounted.

There should only be an exposed pad right underneath the switcher IC as shown the switcher IC's data sheet.  Not that yellow rectangle you have above the center of the IC.

All the other solder-paste openings are correct.  Do not confuse this with the 'solder-mask' which removes the green protective paint layer to expose the PCB copper for connection.

[BrianHG]

you mean the full pad should be exposed? I thought this was the case within the footprint itself...

Glad you made me check, there are more errors.  (It's over 9000)

All the red arrows are errors, the green arrows are correct.

The purple is the exposed solder mask copper while the yellow on top is the solder paste stencil.

You have the switchers whose exposed pad AND solder paste stencil isn't under the 8 pin IC or the right size.
You have D3 by the opamp which for some reason doesn't have any solder paste.

And for the large power connectors, for some reason, the circular pads aren't solder-masked out, but the square pin 1 on them is properly solder masked out.

Now, my old gerber viewer has shown a D-code error on 2 files which may account for the bug, but you need to double check.

Once fixed, I would do a partial flood fill of the switcher IC's heatsink pad to the outer surrounding area above and below the IC to draw away some heat build up.

[BrianHG]

See the shaded green area as an example fill area for each switcher IC.
That shaded green copper fill should match the net of the exposed +VCC power pad beneath so it becomes 1 large filled blob.

[VEGETA]

I used this gerber viewer: http://mayhewlabs.com/webGerber/

and gave me different results. diodes are ok here. Also, I think the connectors are too since they are through hole parts and also solder masked... I remember in kicad that they are solder masked.

check a better render at this gerber viewer too: https://myproto.eu/resources/online-gerber-viewer/

both show the same results, and you got one correct thing which is the switcher heatsink pad.. since it is from the footprint library itself not some render difference.

That shaded green copper fill should match the net of the exposed +VCC power pad beneath so it becomes 1 large filled blob.

I can just create a small copper area (without pads or so) in the green (bottom) layer to do so. but it won't be perfect since the pads of components near it are also on green layer so I doubt it will be that useful. what do you think?

___

Edit: see here https://www.eevblog.com/forum/beginners/small-mosfet-for-capacitance-multiplier-in-a-small-psu/msg3348692/#msg3348692

it shows the through hole connectors being solder masker properly, also on the same page there is a 3d picture for the panel showing it correctly.

[BrianHG]

I can just create a small copper area (without pads or so) in the green (bottom) layer to do so. but it won't be perfect since the pads of components near it are also on green layer so I doubt it will be that useful. what do you think?

I don't know about Kicad, but in Altium, we would call this a 'Polygon Flood Fill', where I would set the fill's net name to the same as the IC's exposed pad and select the feature fill over same net & remove dead copper.  The PCB software would take my rectangular box as a guide and automatically flood fill in all the spare area I marked in green with copper connected to that exposed pad while removing any parts which can not be fitted or connected to that pad.

[VEGETA]

I can just create a small copper area (without pads or so) in the green (bottom) layer to do so. but it won't be perfect since the pads of components near it are also on green layer so I doubt it will be that useful. what do you think?

I don't know about Kicad, but in Altium, we would call this a 'Polygon Flood Fill', where I would set the fill's net name to the same as the IC's exposed pad and select the feature fill over same net & remove dead copper.  The PCB software would take my rectangular box as a guide and automatically flood fill in all the spare area I marked in green with copper connected to that exposed pad while removing any parts which can not be fitted or connected to that pad.

it is 100% in kicad as you said for altium. my point is that it won't be a perfect square due to pads of components near it...

kindly see my above post about gerber issues... what do you think? is it that your software is bad or what exactly? since kicad shows it correctly.

[BrianHG]

Except for the switcher ICs center exposed pad, everything else looks correct in those renderings.

As for the flood fill, all you want is maximum copper fill.  Let the fill hug all the corners and edges, as much as it safely can.

[VEGETA]

Except for the switcher ICs center exposed pad, everything else looks correct in those renderings.

As for the flood fill, all you want is maximum copper fill.  Let the fill hug all the corners and edges, as much as it safely can.

Alright, this is easy. I just need to return from work to do it.

copper zone under the switchers + modify the footprint in order to include solder stencil of the pad under the IC along with the outter portion.

[VEGETA]

Hi

i have modified the footprint to be exactly what we want. under the ic is solder masked + solder paste, while the pad outside is just solder masked without paste.

btw, should I do something similar to the mosfets to be able to solder them properly? I know I can just put them then use the pads and so on to solder them.

I tried making a copper area around the switchers as we agreed, but it didn't produce good results so I scraped it. it only put a little extra area in a random way since, as i said, the area is tight and full of pads on the same layer.

anything else we need? so I can panelize the boards.

I posted the single board gerbers for you on PM.

[BrianHG]

Hi

i have modified the footprint to be exactly what we want. under the ic is solder masked + solder paste, while the pad outside is just solder masked without paste.

You shouldn't have masked out copper above the footprint.  Also, redo the footprint to match the attached land pattern 'EXACTLY', including all 8 pads.  Your footprint is bleeding and oversized compared to the manufacturer's expressly recommended land pattern and it wont mount properly with excess solder everywhere.

btw, should I do something similar to the mosfets to be able to solder them properly? I know I can just put them then use the pads and so on to solder them.

The mosfets are correct.  In fact, that big ' + ' in the paste stencil (but not in the solder mask) in the middle of them is so that the stencil remains strong without gigantic holes and not too much solder will be deposited under them so they may solder down flat & properly.

The advantage of removing soldermask on the other side of the PCB is only beneficial if you were to solder a heatsink on that side of the PCB, but, you also create an open electrical circuit on that side.

You may turn off on the D2PAK's throug-hole pads the solder mask for the bottom side to get rid of that.

To make the flood-fill look better under the switchers, maybe try a smaller gap clearance constraint of something like 10mil and trace thickness of 6mil.  This will fill out and hug the contours around the SMD there much better.

[BrianHG]

I believe that the 'Exposed Pad' paste stencil should be shrunk by 50-80% according to this document.  Or, at least make a similar patter to what you have on the mosfets.  See below:  (Note, this is not the same EPAD SO-8, but a close example.  Approach #1 is the simplest.)

[VEGETA]

I adjusted the entire footprint to be exactly as datasheet. pads are 2.2mm x 0.8mm (was 2x0.6), the thermal pad under it is now as the datasheet says (+-0.01mm) and pretty much you can say it is identical now.

I did modify the tracks to go along with new sizes, not too much done so no problem.

Kindly see the attached images of the switcher footprint mask, paste, and copper. I believe this is correct.

Copper is not so important here as it is straight forward.

Mask is as it supposed to be, all copper pads and thermal pad are exposed (not covered by solder mask). that includes the extra portion of the thermal pad.

paste is the same as mask, although I wanted to exclude the extra portion but thought it won't hurt. What do you think?

_______

As for copper under the switchers, I don't think it is that necessary. we already have thick traces with small area as you see. making such small tolerances to fit a small little blob of copper is not that beneficial and might not be good with pcb manufacturer. scrap the idea.

[BrianHG]

There shouldn't be that extra rectangle pad above the IC.  In the datasheet on page 12 or 15, it says to copper flood fill as much area around the IC as possible.  You will get the most from filling the VCC with my above specifications.
The other pin which will draw heat away from the IC is the GND pad.  You can also do a small flood fill on the right to add copper to pull heat away from the switcher IC.  Copper/tin only pulls heat away if it is directly connected.  The PCB material is actually a good insulator of heat.

As for the paste stencil, shrink that center power tab by 50% in area as my documentation listed above.  If you do not, when JLPCB assembles this PCB, that IC will be floating on a bubble of solder.

[VEGETA]

Done.

I shrunk the under pad and now the extra portion is done. I have made copper filling as datasheet says, as long as I could do it. I didn't modify anything, I mean no trace tolerances or any of that. I don't know how to do it in kicad for a specific area of the board since the rest must be within spec.

anyway, I don't think it is necessary. what is done now should be enough. I believe if we keep looking we won't finish it.

if there are no major issues left, i will send the gerbers to you for final verification before panelization.

[BrianHG]

That looks correct except the paste pad need to shrink by 50-70% in ''square area'' (not length and width).

[VEGETA]

That looks correct except the paste pad need to shrink by 50-70% in ''square area'' (not length and width).

I don't understand.

what square area? I shrunk its size and thus the mask + paste.

[BrianHG]

That looks correct except the paste pad need to shrink by 50-70% in ''square area'' (not length and width).

I don't understand.

what square area? I shrunk its size and thus the mask + paste.

The paste needs to be smaller than the mask for this 1 pad.  The paste adds solder.  Too much solder means the IC will float on liquid metal when baked and will not sit flush on the PCB.  The mask you have is correct.

When I say square, this means if you shrink the paste horizontally by half and vertically by half, the size reduction is 75%.  IE, if your original pad is 4x4mm, it is 16 square mm.  If you make the paste half width by half height of the mask, making the middle 2x2mm, only 4 square mm, you can see you shrunk the square area by 75%, IE 16mm²*0.75 = 12mm², 16mm²-12mm²=4mm².

[VEGETA]

so to sum up, I should keep the current mask as is but make the paste a bit smaller. I don't know if I can match such precise measurements but at least close to them.

the current mask\paste is 2mmx3.5mm. what is the optimal dimensions?

I could make the copper + mask = 3.5x3.5, then make the paste 2.5x2.5 or even 2x2. what do you think?

[VEGETA]

I changed the pad size according to AOZ1284 datasheet (2.5x3.5), then made the mask as its size + a little bit more. Then made the stencil opening less... it is now about 2x2.5.

see the images below, especially the close-up of mask (bronze color)+stencil (cyan blue color).

so, I think this is what your previous datasheet and won't allow the IC to float on blob of solder.

also, the copper for the pad is very good now.

[BrianHG]

I changed the pad size according to AOZ1284 datasheet (2.5x3.5), then made the mask as its size + a little bit more. Then made the stencil opening less... it is now about 2x2.5.

Still a little big.  Make is around 1.7x2.4.

Also, take a look at the attached red arrow..

[VEGETA]

it is now about 1.7x2.4 and the trace is done.