Author Topic: Soft latch MOSFET circuit analysis  (Read 1262 times)

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Offline crypton

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Soft latch MOSFET circuit analysis
« on: February 16, 2017, 09:01:06 pm »
Greetings!

I apologize when this post is rather long, I'm trying to describe how I got, where I got, and derive my questions from there. So please find bold text with main questions and points of interest. I thought to make separate topics for these matters but they are all very related, so I made one big topic.  :phew:

I have put together a modified power switch circuit for an EN pin of a main buck converter. In general, it works as expected, but my concerns are in optimization / finding correct values to meet any criteria chosen (turn off time, inrush currents, overshoots etc). I am not entirely sure, how some sections affect the functionality.
I am basically asking hints and thoughts on If I have made correct assumptions and what else should I analyse and how (smth obvious, parasitic...).

So what is the application:
- Device runs from 15V - 45VDC input. Although mostly using 24V (but should also work <45V)
- The input buck regulator (making 14V for a display) has an EN pin (>1.2V device is enabled. Pin has 180mV of hysteresis).
So to make use of a lower voltage rating MOSFET (30Vds) I decided to switch the EN pin, rather than the direct power input of the regulator.
- Have a Power ON/delay OFF switch. - For "awesome" user experience I looked for circuits where one tactile button switches the circuit ON and, when holding after some time, the circuit is OFF.
- Also the microcontroller can turn the device off.

Used "somewhat working" circuit
[See latch_circuit.png]
[See OSC_commented.png]

Research:
Let me first start off that I first encountered the example circuits from Mosaic Industries Web page from where I got the prototype circuits.

Before registering, I've found several similar circuits and references to topics also in the forum:
Characteristics of a soft-latch power switch
An improvement on the soft-latching power switch.

Simulations:
I've simulated some parts of the examples and my own circuit currently with Multisim 11 in evaluation version, using the DMG6602SVT spice models from the manufacturers webpage.
(Multisim allows interactive transient analysis, which is great)

Find somewhat working simulation files in the attachment.
- load_switch_HV_tap.ms11 - very messy, but works for me (maybe it doesn't for others?)
- clean_latch_circuit.ms11 - tried to clean up the circuit, but this won't work anymore  :-//

Initial condition Set to zero and I use timestep of about 0.001 or 0.0008 to make it run a bit faster (don't need super exact waveforms).

Observations:

Turn OFF time: This is set mostly with R3 and C7.
Problem:
After set RC, the P-mosfet gradually closes. I think it's not a big deal, although voltage on Drain could decay much faster, to minimize losses on the mosfet?
My Solution:
Decrease capacitance for the inrush limit C1. It seems to be affecting the decay time for the P_Drain/output.
This causes another issue.

Auto turn-off: I've read that it's kinda bogus, and I understand the effect. Because of mosfet's internal capacitance, the P_gate is always lower than the P_source, which makes Pmosfet Open during initial transients. (not a good effect for my application. Device can latch and thus switch is kinda pointless). The diode D1 seems to have an important role during this auto-off transient (as explained in the previous sources).

My solution:  I used a bigger capacitance (C8) on the P_Source. This delays the input risetime (with 100k) of the EN input pin and allows P_gate to follow correctly with the input.
I feel it's only half of the story, because the inrush-current-limit capacitor C1 affects this "fix".
Problem:
It seems that the RC with R3 and C1 must be in "some relation" to the RC of R7 and C8 so that P_Drain voltage won't rise above 1.2V during the transient event. I've noticed, both of these go together, but how exactly? Maybe some other solution?

Latch ON / Software off
Latch circuit works quite nicely. The C9 seems to smooth out oscillation when P_Drain reaches 1.2V point. Which is good.
Software off idea is for the main switch to keep held down - after some time software pulls the Nmosfet's gate low, shutting the device OFF.
Problem:
The power won't go OFF immidiately, when main switch is held low for long time though (after software off), it only goes into this force-off.
It's not a big problem, since when user sees the display going black, it releases the button and the device shuts down. Or it could be fixed so that device does turn off immidiately?

Overshoots @45V:
Problem:
When having 45V input voltage, when Pmosfet is closed and releasing the main switch can cause the Pmosfet's base to rise well over 30V (potentially damaging the whole mosfet package).  If I remember correctly I could limit this with R5 or R3, but then all previous issues get affected aswell.

Probably it's not all I've tested and encountered, but most important parts I'd like to understand more.
I hope this info is sufficient (go ahead and ask if smth is fuzzy) and I'll try to clarify.

Thank You for your time, if you've reached so far.  :-+ Can't wait to hear from You!
 

Offline crypton

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Re: Soft latch MOSFET circuit analysis
« Reply #1 on: April 25, 2017, 05:57:09 pm »
I had the circuit implemented a while ago actually and it works very decently (around the RC times, as designed).
So due to this I didn't touch this for some time (so topic died a bit)

But my interest in truly understanding this still remains and so I had some time to actually measure the circuit...

Unfortunately I have now understood that my current scope-probes (10:1) with Rigol's DS1052E 1Meg inputs affects the circuit exactly so that the circuit no longer works |O. (Circuit has 1Meg and 2Meg resistors making the RC).

I would be more than pleased to resolve and update all of the issues mentioned above but due to my measurement, it is impossible. I don't have access to higher impedance (100:1 or smth) probes either.

Any suggestions how could I still measure the waveforms while not influencing the circuit (significantly)?
 

Offline danadak

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Re: Soft latch MOSFET circuit analysis
« Reply #2 on: April 25, 2017, 10:00:58 pm »
Search this forum and google for DIY FET probes. You can do them for a few
dollars. Or use fast OpAmps as unity G buffers. All depends on frequency of
interest, desired Cin, Zin.

http://cds.linear.com/docs/en/application-note/an47fa.pdf



Regards, Dana.
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 


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