spi clock looks bad

[ToBeFrank]

I'm diagnosing why my SPI doesn't work at higher clock rates, and I think it is the clock signal itself. Here is a pic of what it looks like at 3MHz. What causes this and how do I correct it? The only thing on the SCK line is a 10K resistor.

[jahonen]

Are you using long ground clip when measuring?

Regards,
Janne

[ToBeFrank]

Wow, so I pulled a stupid. I had both probes sitting next to each other, but I only hooked up one probe. Turns out I had the ground clip from the wrong probe hooked up! Thanks for pointing me in the right direction.

Does this clock look ok at 12MHz for the SPI to work correctly?

[jahonen]

It looks ok-ish, apart from relatively long rise time, but I think it should work ok. Have you checked SPI clock edge settings (CPHA & CPOL) to comply with the peripheral devices you are using? Also, check maximum clock rates, some devices have quite low maximum sclk frequency limit.

Regards,
Janne

[scrat]

Since there is almost no noise on the clock, could a higher load resistance value be used, to try increasing that slope (i.e. 100k)?
Or could this just be a reason for the clock to generate more noise on the other signals?

[Wim_L]

If this is a standard 10x probe, it may also be loading the circuit somewhat at this frequency (how much depends on the circuit and probe). An easy way to detect if there might be a problem is to simply measure the same with two identically connected probes at the same time, which doubles the loading. If that causes a significant change, the single probe probably is also distorting things a bit.

[ToBeFrank]

Thanks for the replies everyone. I should note that I'm using an unhacked Rigol ds1052e oscilloscope. It has a 7ns rise time so I think this means this 12MHz signal I'm looking at is probably not totally accurate on the scope? I'm going to bring the clock rate down a little so my scope can measure it better and start investigating the other lines on the SPI.

I'm connecting to a MicroSD card and I can initialize it and read/write data when the clock is 150kHz so at least I know it's hooked up properly. I have to level translate the MISO line from 3.3V to 5V with a mosfet because my micro sees a 1 at 3.25V. What parameters on the mosfet should I be concerned about that would restrict the data rate? I have voltage divider on the CS line. The MOSI line level converts using a diode and a 10k resistor to the 3.3V supply.

[jahonen]

I suspect your level translation circuitry causes problems with data transfer timing. Main suspect are those signals which have only pull-up resistor to  produce the '1'-level. Have you tried to measure all your SPI signals simultaneously regarding to the SPI clock, to check which one causes the problem?

It would be perhaps wise to try level conversion 3V -> 5V direction with VHCT/AHCT logic family and VHC/AHC (tolerates higher input voltages than VCC as input without clamping to ESD diodes) for other direction. 74VHC(T)/AHC(T)125 is quite nice for this purpose.

Regards,
Janne

[ToBeFrank]

Thanks. You've given me what I need to know to educate myself about how my current circuit increases the rise times. Not having a hardware/electronic background, this is very helpful. I'm going to redesign my circuit so I can get the full 12MHz clock rate that my micro supports.

I'm looking at a dedicated IC to do the level translation. I'm looking at this IC: http://focus.ti.com/lit/ds/symlink/txb0104.pdf. According to the datasheet, for 3.3V <-> 5V it has a max rise time of 2.7ns and a max propagation delay of 4ns. It has 4 bits of bidirectional I/O. I believe this is all I need to be sure that it will work? Should I send SCLK through this IC also?

[scrat]

Should I send SCLK through this IC also?

Why not?