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| SPI SRAM |
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| David Hess:
--- Quote from: Tom Harker on July 15, 2018, 06:07:25 pm ---As for compression, and this is likely the wrong approach, it will be done in 'real time' so two bytes in, two bytes out - that doesn't really allow for compression as far as I understand it. --- End quote --- Some form of ADPCM (adaptive differential pulse code modulation) may be suitable. At the very least, u-law or a-law compression could be used. http://www.drdobbs.com/database/algorithm-alley/184410326 I see that 2Mbit SPI SRAMs in 8 pin packages are a reasonable cost but 40 Mbits of required storage is going to make that uneconomical leaving some form of Flash memory. I would lean toward either SPI NOR Flash or an SD or microSD card. |
| Tom Harker:
I'm planning on interfacing the SRAM with a micro-controller by SPI, possibly an ATMEGA16 because it has plenty of pins for chip select. I'm using SPI because it is simple and I'm using it elsewhere already. |
| Tom Harker:
I'm not familiar with ordering samples. How does this work? I assume they wouldn't just give away 10 RAM chips? There's a 'comments' input on the ISSI sample request form, what info do they need? |
| Benta:
Greenhorn, eh? Just say you're an engineer hired as consultant on a project for a major company. You're contractually not allowed to say more, except that it's to do with industrial control. You'll get your samples, but expect a phone call at some point. |
| Tom Harker:
I think I'm out of luck on this one, none of ISSI's suppliers have the part and it appears as 'no inventory' on their product list. |
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