Startup issues

[bitman]

Hello - I'm having a puzzling issue which most likely stems from me not knowing enough electroncal theory to explain what I see.  I have a circuit right now on a bread-board only, which has issues when I power it on. That is, unless I have a logic analyzer hooked up, and it starts up correctly. I'm a bit lost to what is going on here - so I'm hoping someone can pin-point my error.



This is a very basic circuit - it's a "work-around" to not being able to find BCD circuits that will show properly HEX encoded 7 segment displays - I've tried to minimize it as much as possible - I have a parallel to serial 4021 and a MAX7219 which does a serial to 7Segment decoding. All controlled with an ATTINY - as the code is very very basic.  Note the bread-board does not have the AVR-TPI programmer interface - so that part of the circuit isn't present.

Here's what I see. When I power on without the logic probe, the MAX7219 remains "idle" - ie. the display is blank. Typically this would be a signal that the chip is in shutdown mode. The first commands on power-on is to initialize the MAX7219 and for some reason this doesn't seem to be happening.  The moment I connect an active logic analyzer to the clock, select and data pins (5 in total - shared clock) everything works! I see the data I expect, and it just keeps working. Here are the signals/labels I have the probes in:

GND (not a signal)
SHARED_CLK
SEL_OUT
OUTDATA
SEL_IN
INDATA

I did scope checks early on - and while the 7segment is not displaying data probing the data lines shows the ATTINY is active and sending the correct data out. Even spying on the initialization code it's sending out the correct/expected commands but the display remains off - the MAX7912 keeps the DIG0 and DIG1 high which is the described "shutdown mode" behavior.

So what's going on that the power-on somehow makes the MAX7219 "skip" but it doesn't when probes are attached?  I'm also not sure where I can find parameters of how long it takes the MAX from power on until it's ready.  The datasheet is here: https://datasheets.maximintegrated.com/en/ds/MAX7219-MAX7221.pdf

For reference, here's a snapshot of a single cycle from the logic analyzer:

[rstofer]

I'm not sure what is happening with those two transistors driving clocks.  Apparently, the bases are always around 5V and the collector can be either 0V or 5V.  If it is 0V, the transistor is reverse biased and there is no emitter current.  If the collector is 5V, the transistor would still be nearly reverse biased.  Somehow, this seems awkward.

Since the clock signal isn't cleanly defined, who knows what happens when things get attached or detached.

Or I'm not reading it right...

[bitman]

I'm not sure what is happening with those two transistors driving clocks.  Apparently, the bases are always around 5V and the collector can be either 0V or 5V.  If it is 0V, the transistor is reverse biased and there is no emitter current.  If the collector is 5V, the transistor would still be nearly reverse biased.  Somehow, this seems awkward.

Since the clock signal isn't cleanly defined, who knows what happens when things get attached or detached.

Or I'm not reading it right...

At some point I'll create a sharable schematic without the addition that I have not yet implemented. The TPI components/connectors are not in play - not on the bread-board. In other words, the pins on the ATTINY are directly connected to the pins on the related chips - no resistors and transistors involved except for R3, R4, and R5 (TPICLK is in other words SHARED_CLK with a resistor R4 pulling it to GND).

With that said, once I get the circuit without the TPI componetns to turn on consistently, I'll have to focus on making the TPI circuit work too. At that point I'll try to fully understand your point.  I attempted to design the PNPs with the specific purpose of disconnecting the TPICLK and TPIDATA signals to reach the chips when the base is high. When the base is low (the default) they should allow signal flow. No amplification etc. - just a semi-conductor based switch.  That said, it's not part of the circuit right now - only the ATTINY is. The diodes and transistors are absent from the breadboard setup.

You also state:

Since the clock signal isn't cleanly defined, who knows what happens when things get attached or detached.

What do you mean by not clearly defined?  Pin 2 of the ATTINY is connected to the clock pins of both the 4021 and MAX7219. It's a pretty clear signal both on the scope and logic analyzer (as I hoped to illustrate by including the screendump from the logic analyzer).

[rstofer]

I was talking about SHARED_CLK and OUT_DATA coming off the transistors as being not cleanly defined.  Basically, if my thoughts on the transistors being reverse biased at all times are correct, those two signals just float in free space.

If the schematic you posted doesn't represent what you have on the breadboard there's not much to talk about.