Beware of ancient and too simplistic MCU SPI peripherals that do not support proper set of arbitrary datagram sizes.
Alternatively, beware of weird SPI slave devices requiring transaction lengths not multiple of 8.
SPI datagram lengths not multiples of 8 are surprisingly common. On MCU side, you would like to see at least 4..16 bit options with 1 bit increments. FIFO mode is a big plus. Working nCS-controlled-by-peripheral is even bigger plus, but STM32 always fails this anyway.
The only way left is to bit-bang, or choose a suitable microcontroller, or choose a suitable ADC (quite frankly, I wouldn't put all the blame to the ST; it's a stupid idea to require 18 clock cycles knowing half of the world's microcontrollers are unable to do it.).
More modern devices in STM32 family support 9-bit datagrams so you can create 18-bit datagram by writing two 9-bit words in succession.
If the slave happens to work with illegal transfer length (16 or 24 bits) by accident, then you are lucky.