STM32G0 Series power supply

[LordyVader]

Hello everyone,

I'm working on a project and have one dilemma with data from the datasheet.


I have issue understanding how to implement this 1x100nF + 1x4.7uF into my design. I figure out it is for decoupling filtering with ceramic capacitors. Here is my schematics so maybe can someone tell me if this is all I need or have to add something more.



And addition question, what should I do with unused pins on MCU, just leave them not connected?

Datasheet I'm referring to is: https://eu.mouser.com/datasheet/2/389/stm32g081cb-1600850.pdf

Thanks in advance for all the help, I'm a mechanical engineer who has to do some electrical engineer job so don't be hard on me if these are the basics.

[Manul]

According to the datasheet you should add 100nF capacitor in parallel with 4.7uF. Physically it needs to be very close to MCU. As short connection to VDD and VSS as possible, especially the 100nF one.

If unused pins are port pins (GPIO), then I recommend to leave them unconnected and set them up as inputs with pullup in software. Or outputs and drive low/high. If the pin is specific function pin - consult the datasheet, maybe it needs external pull-up, pull-down, etc.

[pigrew]

From what I've seen, ST recommends a 100 nF decoupling cap for each VDD pin. The 100 nF should be as close as possible to each pair of VDD and VSS pins. The larger bulk capacitor can be further away. See section 5.4 of the below linked app note for suggested routing.

ST mentions what to do with unused pins in their "getting started with hardware development" app notes. AN5096 states that for the STM32G0 you should have all pins either externally pulled up or down, or internally pulled up or down, or set to be an output. Other MCU models have slightly different constraints (like suggesting to externally tie oscillator pins high or low).

The purpose forcing outputs high or low is to reduce the power consumption of the IC. Pins are always internally connected to the input of an inverter (CMOS nMOS and pMOS pair). These inverters can leak high currents (shoot-through) if the input voltage is around (Vdd/2), hurting power consumption. Forcing a digital I/O pin to be high or low is always a good idea for all MCU. Don't let them float. (analog I/O pins are designed differently, as analog values are expected to be in between GND and Vdd).

In practice, I generally leave the unused pins not connected on the PCB and use software to enable a pull-down. This lets me use them for unplanned purposes if the need arises.

(Read the rest of the app note, too. You'll probably want to connect the nRST pin to a decoupling cap. Also, add a pull-down resistor on PA14-boot0 to set a default boot mode.)

[LordyVader]

@Manul and @pigrew thank you very much. Your answers are very helpful.