Hi Everyone, thanks in advance for any help.
I have heard that running clock traces internally reduces EMI since outer planes act as shields.
Sounds simple but is it always true? What about a 4 layer PCB with relatively thick middle as shown in stackup 1:
Stackup 1:
1 - GND
d1/2
2 - SIG
d2/3
d2/3
d2/3
d2/3
d2/3
3 - PWR
d3/4
4 - GND
Assumptions:
1 - Majority of return current (from signal on layer 2) travels through layer 1 since it is much closer to layer 2 than layer 3 is.
2 - Current travelling through an external plane emits as much EMI as an equivalent amount of current travelling through an external trace would.
Conclusion:
Stackup 1 would radiate as much EMI as if layers 1 and 2 were swapped (signal on external layer).
Questions:
Are my assumptions correct and my conclusion valid?
Is it fair to say a relatively thin middle as shown in stackup 2 would be best for EMI?
Stackup 2:
1 - GND
d1/2
d1/2
d1/2
2 - SIG
d2/3
3 - PWR
d3/4
d3/4
d3/4
4 - GND
Is it ok to use PWR as the return plane? Would stackup 3 be better?
Stackup 3:
1 - GND / PWR
d1/2
d1/2
d1/2
2 - SIG
d2/3
3 - GND
d3/4
d3/4
d3/4
4 - GND / PWR
Would an even stackup (all dielectrics having same thickness) be sufficient?
Looks like stackup 1 is more common than 2/3, is that right?
Would stackup 2 or 3 cost more than stackup 1?
Are there other things I should consider?