I've been scoping all day, but I haven't come up with a solution. The signals look almost identical, and I can't find any indication that something is off, even after reading the SWD specification and timing requirements. If anyone is interested, the SWD protocol is described in the
Arm® Debug Interface
Architecture Specification (ADIv6.0), chapter
B4: The Serial Wire Debug Port (SW-DP). As noted at the very beginning of the chapter, "This specification does not describe the physical characteristics of the SWD interface, such as signal timings." Fortunately,
I found something online here, even though it is related to Arm® DSTREAM. But I think I will have to check the DUT-MCU datasheet again to see if there are any other specifications - maybe general ones, because a quick search in the specification on "SWD" was not very successful.
I have attached 3 trace images and CSV exports for anyone who would like to help me analyze the problem.
Channels (1)/(D1) are SWCLK and (3)/(D0) are SWDIO. The markers are enclosing the "line turnaround" (B4.1.3 in the specs) cycle after the first SWD command right after the first line reset (after switching protocol from JTAG to SWD). The SWCLK frequency for these traces is now at 2 kHz.
- swd_without_LA: Trace when there is only the the Scope attached. Result: OK
- swd_with_LA: Trace when there is the LA attached. Result: NOK
- swd_with_LA_but_10k_in_series: Trace when there is the LA attached with 10k series resistors in line. Result: OK
after scoping the communication between your communication USB device and the DUT and seeing clearly the transitions between the H and Low level are less than ok
I tried external pull-up/down resistors on the breadboard, but that didn't fix the problem. Looking at the oscilloscope trace, I would say that there is no voltage level problem here, i.e. the internal pull-up/down resistors do not seem to be the cause of this problem.
one simple solution we found when we were designing USB-to-TTL communication device [...] was to add on the data lines series resistors
I've already come up with that, but I don't have a reasonable explanation as to why that works in this particular case, since I can't measure or explain the cause of the problem.
By the way, a "simple impedance matching", i.e. line termination, with low impedance resistors does not lead to the desired result. If the chosen resistors value is too low, it does not work anymore.
if your GND rail is not noisy, then your data lines corrupt waveform integrity, as atarodov pointed very well as usual, one trick is adding those resistors
as for me
I must confess, I currently have no idea how to measure fluctuations in ground potential, as I can't tell what to take as a reference on the fly.
Well, if you connect the LA directly to the signal, you basically connect the signal to a R || C element to ground, the input impedance of the LA. If you put an additional series resistor in between, you have R + (R || C).
If you concentrate on high frequencies, which are responsible for the "steepness" of the rising / falling edges, those are dominantly affected by the "C" component of the input impedance. The higher the frequency, the lower the impedance, of course. But with the series "R", the impedance will be at least "R", even if "C" was a short-to-ground.
I can follow you here. But I still can't see why the total capacitive load should be lower when the total resistance becomes higher.
Now, for a real "fix", a closer look at the total signal path will be necessary. It seems to me that the J-Link output can not drive high capacitive loads and that the MCU itself has really strict requirements for the rise/fall time of the SWCLK signal, because for a 1kHz signal, a 20ns rise time would still be plenty fast.
I have not checked the driving strength of the J-Link EDU. I will check on that. As for the timing requirements, I found something, as mentioned a few lines above, about timing requirements. However, I am not sure if the DUT-MCU itself has specific requirements.
I don't know about the input impedance of you LA, but it seems to have a considerable capacitive component to ground, looking at how much it affects the signal slope.
As far as the digital inputs are concerned, I have no clue either. The analog inputs are specified with 1 MΩ || 30 pF.
If someone would like to take the effort to analyze the schematic regarding the digital inputs:
it can be found here.
In my setup, SWCLK is on D0 and SWDIO is on D1. These are pins 16 and 18 of TSW-115-08-F-D-RA in the schematic.
A proper fix IMHO would be a high impedance buffer in front of the LA inputs. Some CMOS buffer might be sufficient, like 74HC126 or something. You can get it in DIP package, you could just add it to your breadboard circuit.
This is definitely a nice solution.
It's either capacitive loading of the signal which is reduced by adding the resistor, or you are getting reflections which again would be reduced by the resistor
I would really appreciate it if you could somehow explain to me how I can verify for sure which of the two problems are actually the case. Somehow the problem has to be quantifiable, doesn't it?
And thanks to all of you who have made so many good contributions so far! I feel like we're getting closer and closer to understanding exactly what's going on in this case.