Author Topic: The mess of FPGA development  (Read 5294 times)

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Offline rstofer

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Re: The mess of FPGA development
« Reply #25 on: March 28, 2019, 04:17:16 pm »
Yes. Of which they will loose considerable amounts if people go shopping on the other side of the hedge because they are fed up with it.

Not really!  Real, paid, designers will always pick the latest and greatest chip because they don't want to design into an end-of-life situation.  Their bosses would worry greatly about obsolescence.

So, chips older than -7 just don't matter.  At best they are maintenance items, not recommended for new designs.  If anybody is designing into obsolete parts, they deserve what they get.  Worst case, dedicate a Win 7 machine to ISE 14.7.  I have a machine like that.  I don't use it much since I built a new go-fast Win 10 machine to support Vivado.  But ISE 14.7 also runs on Win 10 so it's not important.

There's probably nobody on this forum who can cause even a blip in Xilinx's revenues.  We just don't matter in the bigger scheme of things.  They are doing us a courtesy by giving the software away for free.  So, why do they give us the software?

Probably to get more eyeballs on the software.

People can bark at the moon all they want but the reality is this:  New chips, new software.  Old chips, old software.  Pretty simple!  And the moon doesn't care if people bark at it.
 

Offline Ice-Tea

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Re: The mess of FPGA development
« Reply #26 on: March 28, 2019, 04:24:36 pm »
Not really!  Real, paid, designers will always pick the latest and greatest chip because they don't want to design into an end-of-life situation.  Their bosses would worry greatly about obsolescence.

Please. Plenty of markets that can't support the respin of a board or won't tolerate changing a resistor before requalifying or going through acceptance again for the entire product. I *am* a real, paid engineer and I have learned a long time ago that going for the most shiny new toy isn't always the best solution. FPGA lifecycles tend to be a *lot* longer than, say, consumer HW. For fun and giggles I checked on Digikey: Spartan II parts are shown as active.
 

Offline Ice-Tea

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Re: The mess of FPGA development
« Reply #27 on: March 28, 2019, 04:29:35 pm »
There's probably nobody on this forum who can cause even a blip in Xilinx's revenues.

On past projects/employments TI and Broadcom would get their panties wet if we announced a new product. With another employer we had framework contracts with both Xilinx and Altera.
 

Offline rstofer

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Re: The mess of FPGA development
« Reply #28 on: March 28, 2019, 04:36:48 pm »
I'm well aware. But the argument works in the other direction as well: a vendor that supports devices for longer in their latest SW would have an additional notch on their scoresheet while selecting devices which would bind customers more closely ;)

It's the validation that is going to cost a ton of money.  Remember, routing and special features has to be perfect under some set of test designs and it also has to be perfect in terms of all user designs on the planet.  "It used to work under ISE!".  It would cost a ton of money to accommodate these obsolete devices.  I'll stand on multiple millions...  BTW, they also need to bring forward all of the warts and idiosyncrasies.  Why would they want to bring forward all of the warts.  That's what they are trying to get away from.  Start from scratch and leave out the warts!

I liken upgrading large software to poking on an inflated balloon.  You poke here, it bulges there.  You fix one problem and break three more.  At some point you give up and start over.  Just like the old days of FORTRAN:  The best programs were written after the programmer dropped the box of cards.

I doubt companies care much about a scoresheet.  They buy the latest and greatest devices to delay obsolescence.  But everybody knows that things change and it would be foolish to spend the money to add Spartan 2 to Vivado.  I like Spartan 2 (5V IO) and I have a couple of boards but I certainly don't expect Xilinx to add the device to Vivado.  ISE still works fine.  And it would be unfair to add Spartan 3 and not include Spartan 2.  What came before Spartan 2?  Why wouldn't they be included?  Somehow we need to kill off Windows 95 and Windows 3.

BTW, what's the advantage to Vivado over ISE if not for ILA?  The Vivado constraints file alone is enough to drive me back to Spartan 3s and ISE.  What a nightmare!

In my view, the learning curve for Vivado is MUCH steeper than for ISE.  Were I teaching my grandson about FPGAs, I might actually start with Spartan 3 boards and ISE.  At least to get started.
 

Offline rstofer

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Re: The mess of FPGA development
« Reply #29 on: March 28, 2019, 04:55:50 pm »
Nothing in Xilinx's decision says you can't design/buy/support obsolete chips.  You have today what you had then: ISE.  Go for it!

If your product can stand moving forward, well, there's a new toolchain.  Nobody is forcing you to use Spartan 2 for new designs but it you do, you will have to use the toolchain that supports the chip.  What's the big deal?  It's what everybody was using when the device was current.  Realistically, all of the project files will already be compatible with ISE and certainly not Vivado (especially the constraints file).

ISE works, it is still viable, and if you insist on using old devices, it's the toolchain of choice.

I worked in an industry where computers couldn't be upgraded, compilers couldn't be upgraded and source couldn't be changed without a MAJOR verification process.  It was too cumbersome to even contemplate.  So, we stayed with obsolete computers, obsolete compilers and obsolete software because they were PROVEN to get the right answers for our design process.

If you take the purported $200M and 1000 man-years, you can get to $200k/man-year.  Would I believe it would take more than 5 man-years to port the old devices?  Well, when ratioed against 1000 man-years for the project, sure!  I believe it could take 10 or 20 man-years to port the devices depending on how far back they went.  And no matter where they drove the stake, people would be upset that their favorite device wasn't included.

$200k/man-year seems about right, if not a little light.  Figure $150k for wages and 35% for overhead (employer social security, medical insurance, worker's compensation, paid vacations, sick leave, etc).
 

Offline Bassman59

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Re: The mess of FPGA development
« Reply #30 on: March 28, 2019, 04:59:18 pm »
Not really!  Real, paid, designers will always pick the latest and greatest chip because they don't want to design into an end-of-life situation.  Their bosses would worry greatly about obsolescence.

Please. Plenty of markets that can't support the respin of a board or won't tolerate changing a resistor before requalifying or going through acceptance again for the entire product. I *am* a real, paid engineer and I have learned a long time ago that going for the most shiny new toy isn't always the best solution. FPGA lifecycles tend to be a *lot* longer than, say, consumer HW. For fun and giggles I checked on Digikey: Spartan II parts are shown as active.

Another real paid engineer here. We split the difference.

On one hand, we do relatively low-volume long-lifetime products, so the need to support older devices is always there. This means most of us run Windows 7, and we have ISE 14.7 installed next to Vivado. There are a few Windows 10 installs, but the move to that platform is painful for reasons beyond supporting older FPGA tools. Nobody likes it when Windows decides it must install a patch and reboot, borking an overnight experiment. I have a CentOS disk in my machine and can boot it and run the tools on it and at some point that will be my main set-up. (Maybe sooner rather than later if those rumors of Altium running on Linux come true.)

On the other hand, for new designs, we look ahead to what is entering mainstream now. What's the newest device we can buy from DigiKey or Mouser? (Not that we always buy from them, but they're a pretty good indicator of not-huge quantity availability.)

On the gripping hand, if an older design needs a board refresh, we'll look to see whether it makes sense to change to a newer FPGA device. Usually, we don't.

-------------------------

My current project is based on an FPGA device which has been qualified for the operating environment. The vendor's most-recent tools release no longer supports that device family. We have started conversations with the customer about this. Will they do a last-time buy and stockpile the parts? Will they want to qualify that vendor's newer devices? Will they get assurances from the vendor about availability? Lots of questions, no good answers.
 

Offline Bassman59

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Re: The mess of FPGA development
« Reply #31 on: March 28, 2019, 05:04:18 pm »
Not really!  Real, paid, designers will always pick the latest and greatest chip because they don't want to design into an end-of-life situation.  Their bosses would worry greatly about obsolescence.

Also, real paid designers don't give a shit about "FPGA boards." We don't use them, we don't care about them, so whether the latest version of the toolset supports an old board is not important. We just design the devices into our product's boards and go.
 

Offline 0culus

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Re: The mess of FPGA development
« Reply #32 on: March 28, 2019, 05:14:19 pm »
Not really!  Real, paid, designers will always pick the latest and greatest chip because they don't want to design into an end-of-life situation.  Their bosses would worry greatly about obsolescence.

Also, real paid designers don't give a shit about "FPGA boards." We don't use them, we don't care about them, so whether the latest version of the toolset supports an old board is not important. We just design the devices into our product's boards and go.

Exactly...the boards you buy from Intel/Altera, Digilent, etc. are for tinkering. I seriously doubt any of them are used in a serious production device.

BTW, nice username, I have one of those amps.  :-+
 

Offline james_s

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Re: The mess of FPGA development
« Reply #33 on: March 28, 2019, 05:21:47 pm »
Most of the dev boards are targeted at university students. I've seen them used in professional settings in the proof of concept stages or one-off devices for in-house use but they wouldn't be integrated into a product.

I don't really know what the big deal is here though. I use old devices with old tools, so what? If it won't run on Win10 that's because Win10 is a turd, I wouldn't bother updating older software to work on it either, especially when there is a native Linux version.
 

Offline rsjsouza

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Re: The mess of FPGA development
« Reply #34 on: March 28, 2019, 05:23:42 pm »
And as I mentioned before: how much can it really cost them to port it?
The dilemma of removing support from latest revisions of software is not new nor restricted to a single company. The cost of maintaining support is largely due to testing, which tends to become more and more difficult over the years where development boards or devices become proportionally more expensive (when compared to newer generations) and less interesting financially (less incoming money from customers as newer devices replace older generations).

Also, the time where frameworks are changed is the time to make the hardest decisions regarding support. I don't know Xilinx tools very well, but it seems to me the older generations were dropped when the framework that comprised the ISE software was dropped in favour of the newer one (Vivado?). Customers tend to understand such decisions better when there is a major revision of the support software.

There is also the development intricacies: not everything can be easily ported across frameworks. Sometimes things that were developed for a full custom IDE (typical of the 1990s and 2000s) are not easily absorbed by, say, Eclipse or Netbeans. The decision then becomes a very pragmatic one: what can be ported with the allotted money and before the deadline to release device "X"?

I wouldn't even mind if ILA and other whistles and bells weren't supported.
IME this does not work. The confusion created when the new framework has only partial support for specific devices is a big frustration maker and a support burden. Not to say it doesn't happen with newer generations, but any efforts to minimize this with less profitable product lines is certainly a huge benefit.
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Oh, the "whys" of the datasheets... The information is there not to be an axiomatic truth, but instead each speck of data must be slowly inhaled while carefully performing a deep search inside oneself to find the true metaphysical sense...
 

Offline rstofer

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Re: The mess of FPGA development
« Reply #35 on: March 28, 2019, 05:58:03 pm »
One way of looking at it:  Xilinx introduced a new set of chips and a new toolchain.  Old chips continue to use the old toolchain.

I wouldn't be surprised if manufacturers archive the exact version of the toolchain they used to create their product.  I would!  Whatever assumptions were made to get the device working are known to work under the original toolchain.

When I worked for Control Data, we joked about the fact that it cost as much to ship a copy of the operating software as it did to ship the mainframe.
 
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Offline hamster_nz

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Re: The mess of FPGA development
« Reply #36 on: March 29, 2019, 06:15:31 am »
When you have complex tools that are used by only 10s of thousands of people you test it and support for known-good configurations.

Only when you have complex software for millions or billions of users does it get slick as Web browsers....


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Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline bingo600

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Re: The mess of FPGA development
« Reply #37 on: April 03, 2019, 06:03:10 pm »
I just got a new Lappy w. 1TB SSD & 16G Ram.

I decided to install a new Linux Mint 19 (Ubuntu 18.04 engine) from scratch.

As i had to "tickle" Quartus 13.0Sp1 and ISE 14.7 a bit , when i had them installed on my old Lappy -  Mint 17.3 (Ubuntu 14.04 engine).
I decided to install them both in a VirtualBox this time , still using Mint 17.3 in the VM. As this would mean i could just copy the Vbox image to a new machine.

I now have both up & running in Vbox , after a little bit of Vbox USB magic ... (For the programmers)

My "fanciest" is a Spartan 3A , so i have never had use for Vivado (yet)

But both Quartus & ISE works ok on Linux


/Bingo
 


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