This cannot be right?

[king.oslo]

Hello there,

Look at these simulations. The gate of the PMOS is grounded. In the other, I have 5V on the gate. How can I get 5V on the output either way?

Thanks.M

[8086]

Interesting. I had similar result today in multisim (when simulating https://www.eevblog.com/forum/projects-designs-and-technical-stuff/mosfet-power-switch-with-auto-off/msg120110/#msg120110), but since I found many designs online that say this shouldn't happen, in the end I just put it down to multisim being shit.

Maybe it's not multisim after all...

[for some reason, I misread your initial post, your edit is what I experienced with multisim]

[MikeK]

I thought that's how P-channels worked.  You have to appy a voltage at the gate to restrict the flow, otherwise it's fully open?

[king.oslo]

MikeK, after you started typing your reply, I noticed that I had made the error of showing you the wrong simulation. I have updated the thread. Thanks M

[king.oslo]

Here is another one. Watch how the output from the PMOS is higher than the input voltage.

[johnmx]

The simulations are right. Because the drain is floating (hi-z), even the smallest leakage current of the MOSFET will put the drain at 5V. Remember that the voltmeter used to measure that voltage is an ideal one and has infinite impedance.

[king.oslo]

John, which of the three simulations are you referring to? Thanks! M

[johnmx]

John, which of the three simulations are you referring to? Thanks! M

The 2nd one, when the gate & source are at 5V level. That's the topic main question, right?

[king.oslo]

Yes you are right.

Let me see if I understand what you are saying.

You are saying that the transistor is in its non conducting state, but the voltage is at 5V because the transistor leaks current through because the impedance is not infinite. Is that correct? Thanks.M

[jimmc]

I suspect that your post #1 results may be caused by leakage, try adding a high value resistor (100k) from output to ground and see if that makes a difference.

For your last circuit I suspect that is a function of gate-drain capacity which is charged to 5v when the gate is at 0v and then hits the parasitic source-drain diode when the gate is driven to +5v (It would pulse the drain to +10v if the diode were not present). Again you have no DC load so very small currents are needed.

Slow typing I see others have suggested leakage as well.

Jim

[johnmx]

You are saying that the transistor is in its non conducting state, but the voltage is at 5V because the transistor leaks current through because the impedance is not infinite. Is that correct? Thanks.M

The transistor is in non-conductive state, but there is always a leakage current passing through it. This value is in the data sheet of the device.
The drain pin is acting like a small capacitor with almost zero capacitance that keeps charged at the source voltage level. In the real world you cannot verify this because the voltmeter input impedance will discharge this ‘capacitor’.

[king.oslo]

Thanks for that johnmx.

Jimmc, how can this happen? Thanks.M