CE Amplifier Simulated in AWR, Help.

[tec5c]

Hi all,

In one of my classes within my EE degree, we are to "design" a common emitter amplifier that has only the following specs given: Has +10v and -10v power rails, frequency response = 1KHz to 50KHz.

After going through this in class, I don't think there was anyone in the class who was able to achieve the lower frequency cutoff at 1KHz. As there was no more information given there was no real starting point to calculate Quiescent points, component values etc so we were told to play around with component values in AWR and run the simulation to see what effect different values had on the circuit.

I have continued to "play around" with the values and have achieved the -3dB lower cutoff frequency at 1KHz (there's ~0.5dB difference, but that's the best I could get)

My question is, looking at the DC voltages and currents of the circuit, the collector/emitter current is quite low. Should I be concerned about this? If so, how else would I go about achieving the correct frequency response?

I have attached images of the circuit and the freq. response graph.

Note: This is not an assignment, just weekly class work that has no marks supporting it. Just looking for some deeper understanding.

Thanks in advance 

[Zero999]

Increasing the capacitor values will reduce the roll-off. There should be no need to change any of the resistor values.

A lower current means less gain and a higher output impedance.

[tec5c]

Thanks for the reply. I should have mentioned that we have a 1uF max constraint for the caps. I am aware that the bypass cap (CE) does about 80% of the work for the freq. response. But if we are limited to how large we can make this then I could not understand how to get a steeper roll-off.

[Neganur]

C1 and C2 set your lower cutoff, try for C2: 1/(2*pi*1000Hz*8050ohm)= 20 nF  and, hmmm what is rbe in this 2k5? C1: 1/(2*pi*100Hz*2k5||8k) = 84 nF maybe 100 nF, this one can be a little bigger without issues.

Xc3 ~ 0.1*R2 = 0.1*50k= 5k.  C3= 1/(2*pi*1000Hz*5k)= 32nF

[Zero999]

Can't you parallel them or is that cheating?

You haven't mentioned the required gain.

Make RE as low as possible and get rid of the bypass capacitor.
EDIT:
No bad idea because it would reduce the input impedance too much.

[w2aew]

You might enjoy a video I did on the topics several months ago....

[Neganur]

nope, don't get there. 3kHz was as close as I could get.
If you remove the emitter cap, it's easier. Probably too high gain.

[tec5c]

You haven't mentioned the required gain.

There was no required gain specified.

Very simple solution: increase input capacitance.

More elegant solution: recalculate biasing, and increase input biasing resistance. Use multiple stage transistors.

Even better solution: use FET input with really large input biasing resistance.

Ultimate solution (not practical in coursework, but works in industrial): use an op-amp.

I would if I could but we are limited to a single stage BJT, no FET's and no op-amps. 

You might enjoy a video I did on the topics several months ago....

Thanks for the video Allen (sorry if you spell your name different) I have watched that video in the past, and have just watched it again.

If there were more specs given then I'd have no trouble doing this. It's just because we have no given input/output impedance so there's no real starting point to go through all of the DC bias calculations along with the small signal model calcs.

BTW, Neganur what software are you using to run that simulation?


Thanks for the replies guys. I'll keep playing around with the circuit and see how things go, otherwise I'll speak to the teaching staff and see what they have to say about my circuit.

[Marco]

Grounding the emitter for AC is really more something for RF circuits, for these kind of frequencies you set the amplification by the ratio of the collector/emitter resistors ...

You can still use a separate resistor to set the bias current if you want by putting the emitter resistor behind a capacitor (note though that the bias current has to be higher than the maximum expected negative current through the emitter resistor). The cap might get slightly large though (10+ uF in this case) easier to solve it another way here because we are completely free ...

Like someone else pointed out you'll want to set the base voltage lower, to make room for the amplified signal at the collector and also to reduce the bias current.

PS. for a low impedance load you'd generally add an emitter follower, so I just used a MOhm.

[Neganur]

it's multisim from NI. They use some kind of spice version.

With a little work on the bias network I managed to get the 1 kHz lower, but the upper I'm not getting without cheating with a low pass (I did not get Alan's method to work for me, maybe it needs a load?)