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Timer interrupt FIRQ on a 68B09EP

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powerchisper:
Hello friends.

I am not sure what this means.
In the PCB I am trying to fix, the manual says that the CPU has a timer interrupt signal used as a heartbeat for the system.
The clearing of the timer interrupt is done by reading the dip switches ( a 74hct245 to which those switches are connected to  ).

Could someone explain a little bit this "clearing"??

Any help would be appreciated.

johnkenyon:
As a guess,

The output enable line for the buffer is probably triggers a reset (=clear) of a flipflop which is turned on when the counter/timer that does the timer FIRQ times out.

So the FIRQ routine does whatever it does, and then does a dummy read of the DIP switch buffer to clear the interrupt at source, before executing a return from interrupt instruction.

This may seem strange but, it reduces the chip count/complexity of the board.
1) The software will only read the DIP switches when an interrupt is not active, (so there is nothing to reset).
2) It removes the need to decode another address or to decode a write to a specific address - the decoding of the buffer read signal is there already (meaning it is "free", no additional cost)

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