EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: CPaltenghe on November 30, 2022, 08:08:54 pm
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Hi Folks!
I am new to this forum and hoping someone can give me some insights.
I am building a TL494 based push pull circuit to be used in an inverter, but I am not even to the power stage yet.
Scoping the unloaded output of the push pull circuit (see attached screen shot), one can clearly see the erratic pattern.
I do not know where to look for the cause of this.
I have checked for cold solder joints, jiggled the components, tweaked the pots up and down, to no avail.
See circuit diagram and build layout pictures.
Any debugging and places to check advice will be greatly appreciated.
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P.S. There is an error in my diagram, but not on the board. Pin 16 is grounded.
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Put a bypass on VREF. The output control pin is very sensitive to noise. It's not a logic level input, it's... something of a bad hack internally (internal diagrams are actually available for this chip, so this is known).
Tim
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Thank you, Tim.
What does bypass mean to you?
Currently, VREF (pin 14) is tied to 13 (output control) and 15 (in 2-).
Where would I bypass VREF to?
Just a wire, or a capacitor?
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Bypass cap, VREF to GND, near the chip.
Tim
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Thanks again, Tim.
Sorry to be obtuse, but what about pins 15 and 13 that are already tied to 14 (VREF)?
Leave them in place and put a cap from 14 to ground?
Or, disconnect them but tie them to what?
(I'm still learning)
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The net, not the pin. Any will do. There is maybe 10nH between the three positions, not enough to notice or care where exactly you put it.
Tim
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I'm not entirely sure if this is a TI chip or a Chinese clone.
I suppose they ought to be functionally equivalent, but hell knows what devils are in the details...
I would scope all the pins to confirm that the waveforms are as expected. DC where it should be DC, clock where it's supposed to be clock, etc. See how the two outputs correlate with each other.