Hi,
In my project I have 32 analog signals produced from APDs (avalanche photo-diodes). These signals are amplified and split by two for further processing (one branch goes to ADC, other branch goes to trigger circuitry). They are very close to each other in time domain (rise times start very close relative to each others). I need to create a trigger logic based on a simple pattern: Trigger if only one channel is above a threshold, and reject all other cases. I can produce high/low signals for each channel by using comparators and then feed these to some cascaded digital logic elements to obtain the trigger signal. I was wondering if someone can suggest a simpler, faster way. I would prefer fewer number of processing to limit the propagation delays in logic ICs since since the ADC start/stop signal is based on trigger signal.
Thanks...