It's difficult to provide a very clear and specific answer to such a broad question, particularly because the specifics may differ from architecture to architecture. If I was to try my hand at a very general summary of how simple computers work, I'd say something like...
The ultimate source of the control flow is the system clock/oscillator. It starts by itself at power up and drives all the other chips from a control flow perspective, i.e. without a clock they will never advance through their states. It's one of the first things that should be checked after the voltages, if the clock is stopped, unstable or misshapen, none of the other chips can function as a system.
Downstream from the clock, the CPU is usually the main "master" chip, which is to say that as long as it is getting a clock, it will go by itself through all the state changes required to make the system go: it will put a read request on the bus for the next instruction, it will execute it, then post other read/write requests for data or I/O, it will respond to interrupts etc. Other RAM/ROM/IO etc. chips are "passive" in the sense that they will not do anything until the CPU sends a signal. At which point they will go through a few state changes so that they take control of the bus data lines, put the result there for the CPU to read, then relinquish it.
Depending on the architecture, the video controller might also be a master chip vis-a-vis the control flow, since it may need to spontaneously and continuously read the video memory (if shared with the CPU) so as to form a TV signal. Thus, it will also drive the bus so as to issue read requests. There is usually some synchronization mechanism to resolve conflicts if the CPU also wants to read data at the same time (e.g. keep the CPU halted until the video chip gets a byte of data).
So, on a broad level, the flow is clock -> CPU/Video controller -> all other chips. There is usually no DMA controller or other complications in simple computers such as these.
On a smaller scale, especially from the perspective of the bus, things are of course more complicated, each chip can be a "master" for a given clock cycle. All chips that can answer queries (e.g. RAM/ROM/IO) will have to take control (drive) of the bus at some point so as to return the answer while the other chips listen. However they only do so in response to requests, and their "masterhood" is limited to a few clock cycles and usually applies only to the bus data lines.
In a sense, there's no such thing as a "bidirectional" lines. A line transmits data in only one direction at a time, and the current direction, if any, is determined by a strict protocol whose phases we advance through with every clock cycle. It pays to look trough the datasheet of the memory chips and CPU and see their phases of operation. The protocol is often not complicated.