Electronics > Beginners
Troubleshooting Microprocessors
bostonman:
I have a question regarding troubleshooting microprocessors. I'm in the process of fixing a Commodore 64 (this isn't a C64 question though) and experiencing the same problem I've had over the years when coming across microprocessors: trying to measure data and address bus signals.
Basically my question is: what is the flow of a computer section?
A computer section is comprised of a micro, ROM, RAM, and some sort of programmable chip like a PROM. What happens when power is first applied, which chip(s) drive the address bus, etc...?
My difficulty has always been the chips are bi-directional, and all the lines go in and out of each chip. So if say my address bus isn't clocking, which chip(s) drive that bus so I can check whether that chip is getting signals to tell the address bus what to do?
Also, on paper, IC chips (let's say microprocessors) always have some sort of timing diagram. When looking at data and address signals on an oscilloscope, assuming they are working correctly, are always jumping. How does someone look at those signals that are changing rapidly tell whether they are correct?
chris_leyson:
In this sort of situation it's usually good to pulse the reset pin with an external reset generator and use it as a scope trigger. From then on you just probe the processor address and data bus pins looking for stuck drive signals. Then look at chip enable signals and so on. It's tedious and time consuming with a scope so a logic analyser, Saleae for example me gnat be quicker.
ferdieCX:
The easiest way is to build a simple hardware "single step" for the microprocessor, this usually involves using the RDY line to put the processor in WAIT at each machine cycle.
I used to do that when repairing 8080 and 8085 based VT100 and VT102 terminals. Probably you will find such a circuit for the 6502 in the internet.
In the general case, without single step, you have to sync the scope with the MEMREAD or MEMWRITE signals to see what is traveling trough the data and address buses in the "valid" time. As already said, it is a good method to look what happens immediately after pressing the "reset"
It helps to have a ROM burnt with a very simple loop program with few instructions.
David Hess:
--- Quote from: bostonman on December 27, 2019, 01:44:01 pm ---My difficulty has always been the chips are bi-directional, and all the lines go in and out of each chip. So if say my address bus isn't clocking, which chip(s) drive that bus so I can check whether that chip is getting signals to tell the address bus what to do?
--- End quote ---
The combination of the -CS (chip select) and -WE (write enable) signals reveal what each chip should be doing on the address and data bus.
--- Quote ---Also, on paper, IC chips (let's say microprocessors) always have some sort of timing diagram. When looking at data and address signals on an oscilloscope, assuming they are working correctly, are always jumping. How does someone look at those signals that are changing rapidly tell whether they are correct?
--- End quote ---
With a storage oscilloscope the results can be frozen for display. Otherwise a specific signal is selected for triggering which produces a consistent set of results like the -CS or -WE signal to a specific chip. A word recognizer might be used to trigger only on a specific combination of signals.
Sometimes the levels are less important than the transitions or you are looking for invalid levels which does not require a stable display.
atmfjstc:
It's difficult to provide a very clear and specific answer to such a broad question, particularly because the specifics may differ from architecture to architecture. If I was to try my hand at a very general summary of how simple computers work, I'd say something like...
The ultimate source of the control flow is the system clock/oscillator. It starts by itself at power up and drives all the other chips from a control flow perspective, i.e. without a clock they will never advance through their states. It's one of the first things that should be checked after the voltages, if the clock is stopped, unstable or misshapen, none of the other chips can function as a system.
Downstream from the clock, the CPU is usually the main "master" chip, which is to say that as long as it is getting a clock, it will go by itself through all the state changes required to make the system go: it will put a read request on the bus for the next instruction, it will execute it, then post other read/write requests for data or I/O, it will respond to interrupts etc. Other RAM/ROM/IO etc. chips are "passive" in the sense that they will not do anything until the CPU sends a signal. At which point they will go through a few state changes so that they take control of the bus data lines, put the result there for the CPU to read, then relinquish it.
Depending on the architecture, the video controller might also be a master chip vis-a-vis the control flow, since it may need to spontaneously and continuously read the video memory (if shared with the CPU) so as to form a TV signal. Thus, it will also drive the bus so as to issue read requests. There is usually some synchronization mechanism to resolve conflicts if the CPU also wants to read data at the same time (e.g. keep the CPU halted until the video chip gets a byte of data).
So, on a broad level, the flow is clock -> CPU/Video controller -> all other chips. There is usually no DMA controller or other complications in simple computers such as these.
On a smaller scale, especially from the perspective of the bus, things are of course more complicated, each chip can be a "master" for a given clock cycle. All chips that can answer queries (e.g. RAM/ROM/IO) will have to take control (drive) of the bus at some point so as to return the answer while the other chips listen. However they only do so in response to requests, and their "masterhood" is limited to a few clock cycles and usually applies only to the bus data lines.
In a sense, there's no such thing as a "bidirectional" lines. A line transmits data in only one direction at a time, and the current direction, if any, is determined by a strict protocol whose phases we advance through with every clock cycle. It pays to look trough the datasheet of the memory chips and CPU and see their phases of operation. The protocol is often not complicated.
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