Try to understand this electronic load circuit

[chancs]

Dear All,

If you look at the image below, I circled 3 sections with red and labeled them 1,2 and 3. So here are the 3 questions that I want to ask.

Q1. What is the purpose of this 1nF cap? Just there to form a low-pass filter with R3 to reduce input noise?

Q2. In my limited understanding, this 10nF is there to do loop compensation. However, in Scullcom implementation, he also put a resistor in series with that capacitor. So which one is more correct?

Q3. I really don't understand this. Doesn't look like a low-pass or high-pass filter to me.

Thanks,
Sam


Figure 1
Image taken from https://www.eevblog.com/forum/beginners/struggling-with-dc-load/msg2698044/#msg2698044


Figure 2
Scullcom implementation

[GerryR]

It looks to me that "1" is just a decoupling cap to limit noise going into the op-amp which is driving the FET.  (If you do the math, it filters above 30 KHz - hi-freq.  Not sure of "2" though it looks to be a non-inverting integrator drive for the FET to keep the gate drive real steady.  "3" is just an R-C snubber to protect the FET (R-C about 5 uS, if that is 2.2 ohms and not 2.2k).