Remember that current flows in loops. If you have a high speed device, the loop will be something along the lines of:
- Decoupling cap +ve terminal
- Trace from cap to IC VCC pin
- IC lead frame from VCC pin to die
- Across the die from VCC to output driver
- IC lead frame from driver to clock output pin
- External tracking and load
- Ground plane
- Decoupling cap -ve terminal
That's for driving high. When the output drives low, current will flow from the external tracking and load, back
into the driver output, out to GND via the IC's ground pins.
Note to nit-pickers: yes, I've simplified thisThe DC jack and connector have nothing at all to do with the AC current paths. People are sometimes taught that current flows "from the power supply", through the load and "back to the power supply", but that's a gross oversimplification when it comes to high speed design. The "power supply" can be any point on the power distribution net which has low impedance at the frequency of interest.
You should really consider using a PCB with at least 4 layers. Above 100 MHz or thereabouts, the only effective capacitance between VCC and GND is the plane-to-plane capacitance in the PCB itself.
As a worthwhile academic exercise, work out the inductance of 1mm of PCB trace, and therefore, its impedance at 100 MHz.
From this, work out the impedance of the tracks joining your decoupling capacitors to the devices they're nearest to.
Then, work out how to minimise this.