AT cut quartz crystals intended for fundamental frequency parallel resonance, used in a well designed Pierce oscillator circuit aren't that fussy. You can usually deviate from the ideal load capacitance by at least a factor of two, with the only significant side effect of 'pulling' the frequency away from what it would be with the correct load capacitance. In fact in critical applications, it used to be usual to use a trimmer as all or part of the load capacitance on one side of the crystal so the resonant frequency could be adjusted to bring it closer to its nominal frequency.
Also, most PICs have very well designed remarkably robust oscillator modules that aren't at all fussy about your choice of crystal. Problems only usually start when you try to use low power low frequency 'tuning fork' crystals, poorly chosen ceramic resonators, or need to operate at minimum voltage from a battery supply (which wont have significant noise to 'kickstart' oscillation), or at extreme temperatures.
However, you've definitely got lucky as your layout *SUCKS*. Microchip don't provide extra Vss pins (and Vdd pins on larger packages) for fun, they provide them because the PIC needs low impedance ground (and supply) connections. Its mandatory for PICs with multiple Vss pins to wire them all in parallel. Failure to do so can result in various malfunctions or even damage if your application has multiple port pins sinking a lot of current. The same goes for multiple Vdd pins if present.
Microchip quite deliberately put a Vss pin right next to OSC1/CLKIN and only one pin further from OSC2/CLKOUT. Its there so you can connect the crystal load capacitors to it and the OSC pins with minimal loop area thus minimising the risk of disturbance to the oscillator due to EMI or of upsetting its biassing due to surface leakage. You should be able to put the OSC1 load capacitor directly in the breadboard contact strip next to the PIC, diagonally, with one pin in the hole adjacent to the OSC1 pin, and the other in whatever hole it fits in the strip with the Vss pin. The OSC2 load capacitor will go between the OSC2 and Vss strips at the furthest holes from the PIC, bent out slightly so it doesn't obscure the furthest hole in the OSC1 strip. The crystal then goes at an angle from that OSC1 hole to whichever hole is the best fit in the OSC2 strip. If its got very short pins, you may need to extend them. Finally the Vss pin must be connected to ground. Run a cut to length jumper over the top of the chip, from the hole nearest the Vss pin by the OSC pin to the hole nearest the Vss pin by the Vdd pin. If you've got a ground busbar on the same side of the PIC as the crystal, also run a jumper to the busbar. I'd also recommend a 100nF ceramic decoupling capacitor across the Vdd and Vss pins as close to the chip as possible (and for larger PICs with multiple Vdd, Vss pin pairs, one 100nF capacitor per pin pair).
Probing Pierce oscillators with a scope is generally problematic as even a x10 probe presents about 15pF extra capacitance at its tip, which is comparable to the typical load capacitance for the crystal and will cause a significant frequency shift. It isn't unusual to find that connecting a scope probe either 'kills' the oscillator or makes a non-functional oscillator start working. The input pin is far more sensitive to loading than the output pin, and its asking for trouble probing there. One trick is to probe via a series 'gimmick' capacitor trimmed to 1/9 the probe tip capacitance as measured on a good capmeter. With a x10 probe, that gives you x100 attenuation, AC coupled only, and reduces the additional load on the oscillator to a couple of pF.