Understanding Circuit 3.106C of tAoE

[Moriambar]

Hello,
I'm trying to optimize the time I have at work by studying a bit of tAoE.
I'm in chapter 3, page 204 and I'm looking at the circuit C in fig. 3.106, you can find it in the attachment.

Without the pnp tranny Q3, the circuit (essentially fig. B) is designed to drive a high current load via 3.3V logic.
I understand that Q1+R1 form a current sink creating a drop of ~8V on R2, without Q3 this drives Q2 and switches on the load just fine (as long as switching speed is not critical etc).
Unfortunately I don't understand why Q3 should limit current.

My reasoning is this. First of all, when the 3.3V pulse is not applied to Q1, Vce|Q3 = 0, so the transistor cannot turn on. When the pulse is present we have that the tranny can turn on.

When it's turned on... well I think that Vbe|Q3=-0.6V (one diode drop) and this means that ~1A goes through R5 since there's a 0.6V of drop at its 2 terminals and its value is 0.5 ohms.

I don't think this is correct. Most of all, even if it is, how does this limit the current/protect a short (in the circuit after Q2 I presume)?

Thanks

[Ian.M]

R1 and Q1 limit the gate pulldown current to about 180uA. Not coincidentally, that's enough to develop 9V across R2, which is more or less the most that it could be as Q1 collector voltage will always be higher than its emitter voltage.

When Q2 is on, a voltage dependent on the load current is developed across R3.  When it reaches about 0.6V Q3 starts turning on significantly, reducing the gate drive to Q2, increasing its on resistance and limiting the current. Under 1A load current, and Q3 has negligible effect.  N.B. Q2 must be rated for linier operation and over 12W dissipation.

If you can run LTspice at work, some poking around in a sim of it should convince you fairly rapidly, otherwise I guess you'll have to make do with Falstad!

[Moriambar]

R1 and Q1 limit the gate pulldown current to about 180uA. Not coincidentally, that's enough to develop 9V across R2, which is more or less the most that it could be as Q1 collector voltage will always be higher than its emitter voltage.

When Q2 is on, a voltage dependent on the load current is developed across R3.  When it reaches about 0.6V Q3 starts turning on significantly, reducing the gate drive to Q2, increasing its on resistance and limiting the current. Under 1A load current, and Q3 has negligible effect.  N.B. Q2 must be rated for linier operation and over 12W dissipation.

If you can run LTspice at work, some poking around in a sim of it should convince you fairly rapidly, otherwise I guess you'll have to make do with Falstad!

ah I see... so basically it's the Voltage dropped by the 0R5 resistor that turns on Q3, raising its collector voltage towards the emitter, thus shutting off Q2!

Unfortunately I can barely look at this forum while at work (and I have my copy of tAoE handy since working from home). But your explanation is excellent, thanks!