EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: rookie on September 27, 2019, 05:17:07 pm
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How do I understand the concept of drive strength? I work closely with hardware folks and they usually mention this drive strength of io pin or something along those lines. Then I came across this sentence in an app note, where a drive strength is mentioned:
If your system utilizes open collector translation with pull ups to VAUX on the TXD or other UART input signals, you may
have to decrease the impedance of the pull up as the on board translation can require a higher current draw to function
properly, a drive of 1mA will suffice.
May be this question is broad, but what is a good way to understand this concept?
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See the schematic there.
https://www.raspberrypi.org/documentation/hardware/raspberrypi/gpio/gpio_pads_control.md (https://www.raspberrypi.org/documentation/hardware/raspberrypi/gpio/gpio_pads_control.md)
Basically each pin is driven high/low not just by one transistor, but with multiple in parallel. Each of them has a certain ON resistance. The higher you set the drive strength the more of them will be turned on, which means the pin will have less internal resistance, will thus be able to sink/source more current, and given that whatever the pin drives has a certain capacitance that higher current will result in a faster signal rise/fall time.
You want drive strength to be sufficient to have clean enough signals for the required use, but not more so as not to generate super fast edges that radiate EMI for no reason.
On one product I worked on there are fast signals going to a color display and an audio line next to them. Initially there was a ton of noise in the speaker that changed with the display contents, so it was obvious the LCD signals were generating EMI that was picked up by the low amplitude audio signal. Reducing drive strength for the LCD signals to one notch above the minimum for the display to work reliably (was set to max before) eliminated the noise completely.
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As said above some chips have got the option to set the i/o pin drive strength (sometimes as "10MHz/50MHz/100MHz" talking the i/o data rates, or in mA, etc).
On the other hand you may set the drive strength with help of the pull-up/down resistor.
For example I2C bus is an "open collector" system and it requires pullups (a resistor wired from output to Vcc).
With slow I2C bus operation (ie 100kHz clock) and short wires (long wires increase the capacitive load, the output drives an RC then) a 10k pullup would be enough.
With 1MHz clock and 20cm long wires you may need 1k pullups, to push more current into the stray capacitances of the long wires (or into the input capacitancies of many I2C devices hanging at the bus) thus keeping the rising/falling edges of the signals steep enough..
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Thanks for the explainers @Kilrah, @imo! That raspberry pi page link is very useful.
So a followup dumb question based on this comment by@imo:
With 1MHz clock and 20cm long wires you may need 1k pullups, to push more current into the stray capacitances of the long wires (or into the input capacitancies of many I2C devices hanging at the bus) thus keeping the rising/falling edges of the signals steep enough.
How does increased drive current courtesy low pullup(1k) help in fighting the stray capacitance to make the signals steep? I kind of understand that phenomena from a RC time constant perspective.
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Think of it a bit like a selectable resistor in series with the pin. It works very similarly to the gate resistor often used with a MOSFET to prevent ringing that occurs due to the capacitive nature of the load. Stray capacitance can have significant effect at high frequencies and causes digital lines to behave similarly. Just last night I was looking at something on an FPGA board and noted significant ringing, reducing the drive strength ought to lessen this.
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How does increased drive current courtesy low pullup(1k) help in fighting the stray capacitance to make the signals steep? I kind of understand that phenomena from a RC time constant perspective.
It's kind of the other way around. Picture a large metal bell. Now imagine giving it a quick, sharp whack with a hammer (high drive strength), what will happen? Now imagine giving it a slow, gentle tap with the same hammer, what will that do? Going further, a resistance in series with the source could be thought of as a piece of foam or a towel or something between the hammer and the bell, it will absorb some of the impact.
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I kind of understand that phenomena from a RC time constant perspective.
That's all there is to it. When you increase drive strength you essentially just reduce R.
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Hallo all,
In continuation of this topic, how does the change in drive strength affects the GPIO maximum output capacitance?
Surely the increase in driving current would increase the maximum output capacitance?
Thanks.
Rgds,
kakiitek