It's along those lines, but you should include the effect of transistor gm and also Cgd in the analysis when driving a transistor.
Then any voltage gain at either the MOSFET source or drain node will amplify the apparent size of Cgs and Cgd respectfully.
Briefly why :-
This is due to the " miller effect" which is an amplifying/attenuating effect observed on an impedance (usually refers to
capacitor but can also be applied to any Impedance element) that is connected between an input node and another node that
exhibits amplification of that input. From this we get the resultant impedance of any such element Zmiller(Zm)= Z/(Av+1) ,
Which when applied to capacitance is Cm= C(Av+1). where Av= -Av (i.e inverting gain as been defined as positive) .
Lets Apply this to Cgs first, notice that with the feedback node being at the top of Rsource (your R1) this node basically follows the gate voltage (it's a source follower) the voltage gain for a source folllower is Rs/(Rs+(1/gm)) . If 1/gm is small compared to Rs then it can be ignored and Av taken as 1 . Applying this to our Cgs gives Cgs(miller) = Cgs(-1+1) =0 (Yes miller effect can make capacitors smaller or even disappear which is easy to see if you imagine both sides of a capacitor rising and falling at the same rate then the voltage across it does not change and no charge flows into it).
For the above situation in which the MOSFET 1/gm is much larger than Rs (say by a factor of 10 making Av is much less than one which would actually be the more typical case for an high power constant current source/electronic load with a very low value Rs ) then Cgs size will not be effected much and we can ignore miller effect.
Applying the same reasoning to Cgd then any voltage gain at FET drain node would multiply's Cgd : if we had some Resistance in the drain (Rd) then gain at that node ~ Rd/(Rs+(1/gm)) . Here with no Rd Gain at drain Av=0 .
Thus Cgd(miller) = Cgd*(0+1)= Cgd*1 .
So in a common source config with high voltage gain at the drain note that the Cgd (due to Av multiplier) can become the dominant input capacitor even though it's initially smaller than Cgs in your FET's data sheet.
Now compare with a source follower config with no voltage gain at the drain (thus no Cgd multiplier) and a gain at the source
node of almost 1 (non inverting) (here miller effect can make Cgs look smaller as we show above.)
Approaching the subject of stability analysis requires a huge amount of time and effort and you'l face much frustration I've no doubt , it's not for everyone (it's a specialization most would say) but if you put in the effort and crack it you'l be in the low percentage of techies who can actually handle it.