| Electronics > Beginners |
| Understanding the IR2110 half bridge driver |
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| T3sl4co1l:
--- Quote from: ZeroResistance on April 06, 2019, 05:10:38 pm --- --- Quote from: T3sl4co1l on April 06, 2019, 06:45:07 am ---Estimating gate rise/fall is very easy. Take Qg(tot), divide by Vgs(on) (typically 10V) to get Cg(eff). --- End quote --- Why do we take Vgs(on) here instead of the actual gate driver supply voltage?. I mean if we are providing the gate driver a supply of 15V should we still consider Vgs(on) of typ. 10 for the above calculation? --- End quote --- Because that's what the parameter was measured at. You should indeed prefer the equivalent under your conditions. For this, you might consider the gate charge curve instead. Downside: that's a typical plot, not max. The extra voltage adds charge above the Miller step, where capacitance is constant (Vds ~= 0), so the change will not be considerable. Presumably, you can take the max value, and scale it by the same amount. Say there's 40nC (typ) at 10V, and 52nC at 15V. Say max (at 10V) is rated 64nC. We then guess max at 15V is (64/40) times 52nC. Using max charge is relevant to power supply consumption and dissipation (the charge is drawn straight from the supply, and dissipated through the driver's resistance, and R_G). Driving a 64nC gate at 200kHz requires 0.064uC * 0.2MHz = 0.0128A (micro cancels with mega), or 12.8mA. The resistances dissipate that much times the supply, or 12.8mA * 10V or whatever. (There's a 1/2 in there when you calculate the energy lost in charging a capacitor through a resistor -- however, that energy comes right back out again, so the energy over a full cycle is one times. Easy!) You should probably use typical, or maybe even minimum (if given), charge, for rise time calculations, since that affects the next phase of design: parasitics in the switching loop. You want the sqrt(switching loop stray inductance * junction capacitance) (mostly transistor Coss, or including diode Cjo for the buck/boost case) to be much less than the rise time, otherwise it is likely to resonate and generate voltage spikes and emissions. Often, this conflict is unavoidable, and then damping or snubbing is necessary. --- Quote from: ZeroResistance on April 06, 2019, 09:03:17 am ---This is mind mindbogglingly amazing!! You never cease to amaze me T3sl4co1l :-+ I'd like to hear your story, regarding you journey to master your trade, if you have a blog or something pls do share. --- End quote --- Thanks. Was never one for blogging, but I did write webpages back in the day, https://www.seventransistorlabs.com/tmoranwms/Electronics.html which is chronologically about highschool to college days (unfortunately I didn't date most of the pages, so you'll have to guess when anything was written). Newer pages are on my main site, like some projects here https://www.seventransistorlabs.com/Projects.html . The calculators are particularly useful. I haven't added any pages in a while, unfortunately... --- Quote ---BTW I was looking to drive various configurations of Half bridge one is the standard one, and one is with dual supply, how would you drive the mosfets in a dual supply Half bridge configuration, they would need transformer drive , correct? --- End quote --- Use a bootstrap driver referenced to the lowest supply. If you need ground-referenced logic, add digital isolators or level shifters there. Unfortunately, no one makes a bootstrap gate driver that goes negative. I guess it wouldn't be bootstrap anymore either, so that figures. It could maybe be solved with a synchronous diode, to mimic a bootstrap diode but upside down. Else, there's the full isolator circuit, which is a whole lot more bother, and is also a different market segment. (There are some AD and TI isolators with integrated DC-DC converters that would be very attractive here.) --- Quote from: MagicSmoker on April 06, 2019, 11:09:05 am ---2. I generally roll my own gate driver circuits using a variety of approaches depending on power level, how high an isolation voltage is required, etc., but for a beginner I would recommend using an isolated gate driver IC like made by Silicon Labs* or Analog Devices' ADuM series, etc., and one or two small 1W - 2W potted dc/dc converter modules for supplying isolated power to the upper and, optionally (though highly recommended) lower switch gate drivers. --- End quote --- In other words, like this. Note that SiLabs parts aren't rated for DC consistency, or at least none last I checked. The trick with all of these devices (gate drivers and digital isolators), is they only communicate in pulses. There's a latch on the high side, and it's set or reset when a rising or falling edge is received. If no edge is received but noise upsets the state, now you have opposite logic states across the isolator until the input makes a complete cycle. The ADuM parts claim to use a ~10s µs refresh, with a default dead-line condition if no pulses are detected (a missing pulse detector). I'm not sure about the TI parts. This makes me leery of SiLabs parts (and maybe TI) for lower frequency, non-error-tolerant applications (like gate drives), but the others seem okay. Incidentally, if using optoisolators, be very careful of the isolation dV/dt and voltage step ratings. 6N136 for example is often rated very differently from others (lots of V/us, but at a step of like 5V, of course it's not going to do anything!). SFH6345 is the preferred equivalent: basically a 6N136 with better shielding and no base pin connection (which is where most of the dV/dt coupling occurs). Integrated logic receivers (like 6N137 and various HCPL and other devices) are usually pretty good. If you want a more integrated device, there are optos with full size MOSFET (and IGBT!) drivers included. And by IGBT, I mean, higher voltage rating, lots of amps output, options for external drive transistors (so there's actually two smaller gate drivers inside, to drive those, to drive the IGBT), desat protection (fault feedback), soft shutdown and so on. The full featured part I think is like $10/ea -- but this is a hell of a lot cheaper, and smaller, than rolling all of that yourself. It's a good deal! Anyway, I digress; --- Quote from: ZeroResistance on April 06, 2019, 05:56:43 pm ---Just looking into the math here. Time const = 6ns Driver rise time = 25ns RMS sum = sqrt((25^2 + 6^2)/2) = sqrt((625 + 36)/2) = sqrt(330.5) = 18.18ns rise time Would this be correct instead of the above mentioned ~12ns rise time --- End quote --- Oops, I should say vector sum, if that's meaningful. Or RMS sum as opposed to RMS mean. So really, just RS. Or RSS. Not RMS. :-DD In short, rise times stack (a filter chain is always slower than its component parts), but they don't add arithmetically. For loads over 1nF equivalent, it's probably fine to use just the RC time constant, and ignore the driver intrinsic speed (which will be much smaller than the time constant). Tim |
| ZeroResistance:
--- Quote from: T3sl4co1l on April 06, 2019, 07:37:21 pm --- Oops, I should say vector sum, if that's meaningful. Or RMS sum as opposed to RMS mean. So really, just RS. Or RSS. Not RMS. :-DD In short, rise times stack (a filter chain is always slower than its component parts), but they don't add arithmetically. For loads over 1nF equivalent, it's probably fine to use just the RC time constant, and ignore the driver intrinsic speed (which will be much smaller than the time constant). Tim --- End quote --- Many thanks for the extended reply and the links provided. So, how does one calculate the vector sum or rss? The IRF540 has a Qg(tot) of 71nC, so that gives it a C(eff) of ~7nF at Vgs(on) of 10V. So in this case is it fine to ignore the driver speed? |
| T3sl4co1l:
Just sqrt(a^2 + b^2 + ...). The Pythagorean distance, if they were dimensions. Yeah, ~7nF is enough not to worry about it. Tim |
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