Understanding Voltage Rails in High-End Processors

[Freshman]

I have observed that high-end processors typically operate at relatively low voltage levels, often around 1.2V or even lower. I am curious to understand how such low voltage levels are sufficient for the operation of these devices.

Through my research on this forum, I have learned that CPUs generally have multiple power rails, such as those for the core and I/O, each operating at different voltages.

I would like to gain a deeper understanding of the reasoning behind using separate voltage rails for the core and I/O. Additionally, I am interested in knowing which of these rails typically requires higher current and the underlying reason for this higher current demand. Any insights would be really helpful.

[rstofer]

Internally, semiconductors look a lot like capacitors as do the interconnects.  It takes time to charge/discharge capacitors so the lower the voltage change, the faster the device can change states.  And then there is heating due to the driving impedance.

The smaller the feature size (transistor cell), the lower the capacitance and the faster it will switch.  That's why CPU speed is inversely proportional to feature size and that's also why CPU speed has increased so much with improved manufacturing techniques.

IO voltage levels need to be high enough to interface with external logic or drivers.  It used to be that 5V was the common answer but these days it is 3.3V

[AnalogTodd]

I have observed that high-end processors typically operate at relatively low voltage levels, often around 1.2V or even lower. I am curious to understand how such low voltage levels are sufficient for the operation of these devices.

Through my research on this forum, I have learned that CPUs generally have multiple power rails, such as those for the core and I/O, each operating at different voltages.

I would like to gain a deeper understanding of the reasoning behind using separate voltage rails for the core and I/O. Additionally, I am interested in knowing which of these rails typically requires higher current and the underlying reason for this higher current demand. Any insights would be really helpful.

Processor cores are run at the voltage levels they are for one main reason: power dissipation. Processor speed is determined by how fast you can switch logic gates and the logic gate switching takes current to drive the gate capacitance of the transistors. Going faster requires more power: P = 1/2 * f * C * V² is the formula for dynamic power needed. Controlling the power is easiest done by lowering the voltage. On top of this, cramming more transistors into a processor pushes one to smaller size devices. This ends up dropping the thickness of the gate oxide on the transistors and lets them operate easier at lower voltages. The core is where the most current is required--makes sense as this is where the computing is done. A lot more transistors running whatever code you have; currents for processor cores are now in the hundreds of amps at voltages less than 1V.

As to why the I/O would run at a different voltage, the reason is noise immunity. You have the processor needing to talk to outside devices and each device may be from a different fab lot, fab, or manufacturer and you don't want to be losing information, so higher voltages allow for wider limits defining a '0' or '1'. Everything on the processor itself all runs the same. Considering the I/O is just a small bit of circuitry to interface between the core and the outside world, this is a much lower current requirement.

[Berni]

Lower the voltage the less charge it takes to take a trace (and FET gates) of given capacitance between logic high and logic low states.

So they optimize the transistors in high end digital chips to work at these voltages, you can make a FET switch at any gate voltage threshold, based on how you dope it, even down into negative volts (those are typical called depletion mode MOSFETs). Also these low voltage allow them to make a smaller transistor (less breakdown voltage needed, hence FET channel can be shorter)

For IO these voltages are often too low to be resilient enough for reliable operation, so they tend to use higher IO voltages.

Yet despite all this optimizations the typical CPU or GPU can eat somewhere around 50A to 300A on the core supply rail.

[11mrjones]

Integrated circuit technology is always trying to reduce the size of devices in order to cram more capability (number of devices) into smaller and smaller footprint (die size). And smaller devices can run faster as mentioned. As you approach a mosfet  gate length (~ distance between source and drain, ie, channel length) of 1um down to 10nm and below the problem becomes one of leakage current, ie, the ability to turn off the mosfets. This is the crux of the problem, at smaller and smaller dimensions you can not turn off the mosfets. This is why these chips now run so hot. You have fets with tiny leakage currents (source to drain @ Vg=0) but now millions and millions of them, hence , for total leakage we are now talking amps when the IC is not even on/running. How can you reduce the leakage, yes you need to lower the operating voltage (besides other clever techniques). With the drain and source distance continuously shrinking, leakage becomes more and more of a problem. Leakage of even 1 nA becomes a problem because you now have millions upon millions of devices. It is a problem of power dissipation.

At 1 um gate length (~ the distance between the source and drain) you could operate at Vds=5V because the gate length is large enough that leakage between the source and drain is acceptably low when the device is off (Vg=0V). Now imagine shrinking further, say to 10 nm gate length. Now the source and drain are so close together that at 5V leakage is way to high, power dissipation is through the roof, you can't keep the chip cool, etc. So you need to reduce Vds to say 3.3V, then to 1.5V, then to 1V,  to be able to turn off the device sufficiently (ie, with an acceptable amount of leakage current between souce and drain when Vg=0V). At small enough feature size (say <10 nm) you completely lose control of the channel between the source and drain via the gate (ie, via Vg) and you then move to a different architecture, ie, from a 2D device (normal planar fet structure to a 3D device (FINFET: structure where the gate now wraps around the channel in a non-planar 3D arrangement in order to gain back more control over the channel in order to be able to turn it off.)  This is now where the operating voltage is also approaching a lower limit, you can't run at 0V.

If you can't turn the device off then you don't have a switch

[SteveThackery]

Correct me if I'm wrong, but one key factor is that modern processors use FET technology, so there are no 0.6V semiconductor junction voltage drops to worry about. It would be challenging to build a processor using bipolar transistors with a supply voltage barely able to push current through two junctions in series.

[11mrjones]

Power consumption and scalability. Bipolar (continuous base current when on) is much more power hungry than cmos, more difficult to scale to smaller dimensions than cmos, cmos integration is easier for a variety of reasons in general.

[dkfan9]

Interesting that as MOSFETs get smaller, they draw more gate current.

Perhaps illustrative of other challenges as voltages and dimensions decrease, the failures in Intel processors the last couple years were primarily related to excess voltage.

[11mrjones]

Not more gate current. More current between the source and drain when the device is supposed to be off, ie, Ids at Vg=0.

[Konkedout]

Coincidentally, have a look at this article.  Maybe this is extreme high end:

https://www.electronicdesign.com/technologies/power/article/55262555/electronic-design-16-phase-pwm-controller-regulates-power-to-ai-chips-in-data-centers?o_eid=9250I5733801H2N&oly_enc_id=9250I5733801H2N&rdx.ident[pull]=omeda|9250I5733801H2N&utm_campaign=CPS250318153&utm_medium=email&utm_source=ED+Power+%26+Analog

[dkfan9]

Not more gate current. More current between the source and drain when the device is supposed to be off, ie, Ids at Vg=0.

My understanding was that both happen--increased D-S leakage current and increased gate current via gate oxide tunneling.

[11mrjones]

Yes.... gate oxide current leakage also increases as devices shrink, due to quantum mechanical tunneling through the gate oxide layer. This is a result of the need to reduce the gate oxide thickness,  as gate length shrinks, to maintain control of the channel between the source and drain. Down at, say, the 10nm node your oxide is so thin that you get the onset of tunneling, a quantum mechanical phenomenon that is largely dependent on the oxide thickness. At this point the gate oxide material, silicon dioxide, is replaced by hafnium oxide. Hafniun oxide has a much larger dielectric constant than silicon dioxide, hence you can make the layer thicker and still maintain the same gate to channel capacitance which you need at a certain minimum level in order to maintain control of the  channel between the source and drain.  Now since the oxide layer thickness has increased the tunneling (gate current leakage) current is reduced since it is largely thickness dependent. So, true, gate current can increase, but this is ***orders of magnitude*** lower than that from source to drain leakage. Drain to source leakage, and the concomitant increase in power dissipation, is the main problem/reason driving Vds lower as referenced/infered in th original comment/question. But you are correct also with regard to the problem associated with Igate.

[dkfan9]

Thanks for the detail Mr. Jones!

[MarkT]

Its interesting to note that the individual FETs and logic circuits in these processors work in a regime far from what you experience in a human-scale circuit.

For instance stray capacitance is measured in femtofarads, i.e. 10^-15 farads, FET on-resistances in kohms, and dV/dt's in V/ps (volts per picosecond).

So in the classic CMOS dynamic dissipation equation an example (made up) calculation might be:
P = NfCV^2, N might be 10^8, f = 10^9, C = 10-15, V = 0.6, giving power = 36W... 
Just raising the voltage from 0.6V to 1V would raise that to 100W...   Clearly minimizing supply voltage is a big win.

In practice N, the number of actively switching devices, is a lot smaller, and the static dissipation from leakage would be a considerable fraction of dissipation.   

Tunnelling leakage currents rise exponentially with voltage, so low supply voltage is extremely important for static dissipation as well - the story is the same lower voltage = better performance.

Static dissipation can only be reduced by switching off power to circuit blocks when they are not being used.  This is extensively done in modern processors I believe, and there are a whole host of tricks used to improve performance.  For instance voltage and clock speed can be dynamically adjusted to suit conditions.

[MrAl]

I have observed that high-end processors typically operate at relatively low voltage levels, often around 1.2V or even lower. I am curious to understand how such low voltage levels are sufficient for the operation of these devices.

Through my research on this forum, I have learned that CPUs generally have multiple power rails, such as those for the core and I/O, each operating at different voltages.

I would like to gain a deeper understanding of the reasoning behind using separate voltage rails for the core and I/O. Additionally, I am interested in knowing which of these rails typically requires higher current and the underlying reason for this higher current demand. Any insights would be really helpful.

Hello there,

The simplest answer is that the power dissipation goes up as the square of the switching voltage Vs.  So approximately P=K*Vs^2.

There is always resistance in series with the cap, either from the switching device or from the cap ESR, and that total resistance dissipates power.  The amount of power dissipated is lost as heat and heat is a problem in small packages because the temperature rise goes up as the total surface area goes down.  This means a more efficient heat sink would be needed, and more careful design of the CPU layout.

The relationship to the voltage is simple.  The power goes up as the square of the switching voltage Vs: P=K*Vs^2
This means that as we lower the voltage, we dissipate a lot less power.

For a circuit working at 5 volts the relative power dissipated in the total resistance would be K*5^2 which is P=K*25.
If we lower the voltage to 3.3 volts, the power dissipated in the resistance would be K*3.3^2, which is P=K*10.89
If we lower the voltage to 1.2 volts, the power dissipated in the resistance would be K*1.2^2, which is P=K*1.44
Note that when we go from 5v down to 1.2v we reduced the total power dissipation by a factor of about 17, which is a huge amount.  That means, for one example, we can make the total package size one-seventeenth of the size required at 5v, or put more transistors into the original package.
Even when we go from 3.3v down to 1.2v that's still a factor of about 7.6 which is still a lot.  That allows more transistors to be put into the same package.

Noise immunity is a separate issue which is harder to deal with than voltage, but because of the huge benefits of lowering the voltage we develop ways to deal with that one way or another.

[11mrjones]

"The simplest answer is that the power dissipation goes up as the square of the switching voltage Vs.  So approximately P=K*Vs^2." I agree with that statement as this aligns with the question in the OP. I think that I jumped from a cicuit/uP perspective to more of a device perspective due to my bias/history in dealing more with technology development on a device level. I was concerned with ensuring a working fundamental device (xtor) that meets certain fundamental device terminal characteristics as a first requirement/step. From a device perspective we needed to figure out how to make a working device as it shrinks. However, what good is a new/smaller device if you can't make a better/faster/smaller product/circuit/uP that people want. A bit of a chicken and egg maybe. Historically you took fundamental features and characteristics and scaled them by X, ie, gate length, tox, Vds, metal layer pitch, etc, but that scaling has been broken for a while as the fundamental limit on device feature size is/was upon us.     

[u666sa]

how such low voltage levels are sufficient

The smaller the architecture the lower the voltage.

I would like to gain a deeper understanding of the reasoning behind using separate voltage rails for the core and I/O. Additionally, I am interested in knowing which of these rails typically requires higher current and the underlying reason for this higher current demand..

The lower the voltage the more current you need.

Note how power demands did not decrease with lowering voltages. It used to be 200W PSU was top of th eline, nowadays 1200W or more is norm.

So the power is there. However, the voltage required to trigger circuits is lower, because the gap is much smaller. The gap between transistors is measured in nanometers. Frankly something like 5 volts (and none significat amps) will bridge the gap and burn the circuit inside CPU.

[amyk]

Relevant to this discussion is that you should never check for shorts on the power rails of a mobo with the CPU mounted for two reasons: the typical DMM test voltage of several volts far exceeds the absolute maximum specified for any recent CPU, and the static resistance is extremely low; consider a CPU that has a Vcore of 0.8V at idle with all the clocks stopped, and consumes 1W - that's already 1.25A, or an equivalent resistance of 0.64 ohms. Incidentally, this also means several-ohm shorts between the VRM outputs and ground have very little effect on its operation, except perhaps a little extra heat generation.

[Berni]

You can measure resistance on the Vcore rail of a CPU or GPU.

There is no problem with "overvolting" it because the static power consumption is so huge that it will drag down the test voltage on any reasonable multimeter. But as a result you do measure very low resistance on these rails, so if you see a few Ohm to ground that is actually a good sign. When they blow up this resistance drops down into the 10s of miliOhms and this is one way to tell if you got a completely dead core that is not worth further troubleshooting.