What is going on in this 4 layer PCB?

[davegravy]

I'm studying the PCB design of the evaluation board for the LTC2512-24 ADC (24-bit). The second layer seems to be a solid ground pour, but the third layer is interesting. See attached, or get the design files from Analog Devices here.

Voltage regulators are along the top of the board and each voltage is brought vertically down the board to the components that need them using this 2nd layer. It seems there's a small ground trace between most (but not all) power sections. What is the purpose of this? Is this to prevent supply ripple/noise from one regulator polluting another? Isn't it a problem if any supply section has noise in a design like this? Why do some power sections lack this trace between them?

In most of the places where this ground trace runs there are frequent vias connecting the trace to the 1st/2nd layer ground -why? One noteable place where these vias are absent is where the ground trace makes an "S" curve, about midway down the board to the left side. Why the "S" shape here and why the absence of vias? This is approximately beneath the ADC driver / diff amp if that matters. Would the designer have preferred to continue the vias but didn't want to use blind/burried vias for cost reasons?

Lastly, on the 4th layer there is a ground pour just locally around the analog section of the board and a second local one around the underside of the FPGA, contrasting from the top and 2nd layer which has a ground pour over the entire board.  Why separate local grounds instead of globals like on the top and 2nd layer?

[T3sl4co1l]

Yes, I would assume so.  At least just from a glance, not looking into the complete design.

The mid-left squiggle is probably just too cramped to get more vias in there.  Your screenshot doesn't show the component placement but I'm guessing there's simply stuff in the way.

The frequent vias really don't matter here, as they're spaced close enough (the 'S' aside) to give a cutoff of some GHz, maybe 10GHz or so.  (That is, for the vias stitching traces, the loop length corresponds to a folded dipole or slot antenna structure, with a cutoff somewhere up there.  For vias stitching planes, they act as the sidewalls of a very shallow waveguide, so, the impedance is quite low to begin with (due to the wide aspect ratio plus dielectric loading), and also the cutoff is quite high.  (Also the transmission rate is quite low, because FR-4 is fairly lossy up there; but that's not too important here.)  Down at frequencies relevant to the converter, any possible error due to currents flowing in these loops will be reduced asymptotically from their resonant figures -- that is to say, if a given pair of vias and trace or plane is resonant/transmissive at say 10GHz, then it'll be ballpark something like -60dB at 10MHz, and so on.  (For a waveguide it'll be worse than that, because the transmissivity is a length weighted figure.  But we can model a simple trace loop or whatever as an LC circuit, in this case where C is small enough to ignore so the L is all we're really concerned with.)

I suppose, with a SAR (huh, didn't know they made SARs in that many bits -- impressive -- granted, I haven't shopped for fast 24-bit converters at all, either), this will be highly sensitive to noise at a rate comparable to the clock frequency (or sampling aperture, or anything else relevant), so such a degree of stitching may well prove fruitful here -- ordinarily this would be complete overkill for anything other than RF, but the thing is, when such microscopic (indeed nanoscopic) errors can be detected, even the tail of that below-cutoff stuff can matter.

Anyway, it's also not that there's a whole lot of noise on those traces in the first place, or probably the planes either, and the ground (guard?) traces inbetween them is just an exercise in [gestures rudely].   To be sure, you'd have to model it in some reasonable way (this could perhaps be SPICEd, but you need to represent the board somehow, even if just local regions of it -- and test that against expected noise currents and paths, and determine whether the generated voltage is enough to worry about; else, a full-field simulation could be done, at significant expense, e.g. HFSS), or build multiple variants of the board and test them.

Likewise the middle-right hook-like section without guard traces, is probably just because there's not enough space to do it otherwise.  maybe that would be better routed on another layer, or differently at all; which... looking at it, actually, the area is surrounded with the one-from-the-right pour on the top, right, bottom and left edges, and only a few vias are picked up scattered in the middle by the rightmost pour; perhaps it would be better with a direct route (notice no connection is made on the horizontal or vertical sections on the way to the middle of this (FPGA?) component!); and perhaps some (GND or signal?) vias could be moved around to get a wider route, escaping through the top-right corner of the component (where there's one lone via -- but more width already than where the top-left via is surrounded by unconnected vias, making an even tighter choke point there!).

Even this, I'm guessing, doesn't matter much; if that's an FPGA, then that's probably Vcore or something like that, where ripple might cause timing error (jitter), but nothing important for analog purposes.  I'm also guessing they have bottom-side bypass caps studded around the thing, as is the usual style; so that the route length for this pour doesn't matter very much, anyway.

The one thing that does stand out, is that fat trace in the middle (hm, also why is it solid black?); that usually reflects poor routing decisions, or just an outright shortage of layers.  But if it's away from sensitive signals, and it's well-filtered power or something, y'know, and not causing trouble for where it's cutting through (which, probably not, looks like that pour only connects to two pads at the center mid-bottom there?), then yeah, who cares right.

...Actually, what the hell is that middle pour even doing?  It's got five vias up top (presumably power (LDO thermal pad?) and bypass cap?), I don't see anything else along the way, and then two pads all the ass way at the bottom.  Could this not have been routed on the bottom layer or something, as an ordinary trace?  If this is right under the ADC, surely it would've been preferable to leave this area just, like, GND on several layers or something?  Weird...

Well, presumably this board is getting the full capability of the chip, so it's not like these are fatal errors -- like I said, the stitching is generous, presumably the bypass/filtering is adequate, and the component placement is probably good enough, so they're not exactly throwing away LSBs with this kind of stuff.  It's more of a style thing, and it's really just a bit perplexing seeing so few connections to a pour, why allocate it at all in that case -- but again, I'm just looking at the one layer here, maybe it's deep enough in the stack that it doesn't matter, maybe routing on other layers sucked anyway, etc.  The kind of design decision that's less elegant, more cromulent.


As far as outside (top/bottom) pours -- these aren't usually of much value to begin with, because the lateral (edgewise) coupling between traces or pours on outside layers is quite modest.  That is, consider two parallel microstrip traces, with say 7 mil dielectric to inner plane, and 7/7 width/space for the traces.  This gives a coupling factor something like -- y'know, I haven't looked this up in a while, do look it up if you need the exact figure -- ballpark 15 or 20%.  That is: for example, if you look at the normal mode vs. (differential mode / 2) impedance, of differential microstrip of these dimensions, you see differential being only some percent less than the normal mode, or than similar geometry of a lone microstrip trace.  This says that the traces predominantly act alone, and the coupling between them is only modest.  (So it's kind of a myth to call it "differential routing", but it's not actually important how well coupled the traces are, as long as they're length-matched over any disturbances they might pick up -- differential routing is more about canceling noise than any particular matters of common-mode impedance or coupling.)

So, likewise the case for microstrip vs. CPWG (coplanar waveguide with ground -- microstrip with ground poured around it), for similar dimensions with/out the same-layer ground, the impedance is only reduced by a modest amount, say 10 to 20%.  Which is what we're looking at here [I assume], with ground poured on top/bottom, around traces or components (pads).

The other things such pours do for you, is: reduce the general ground impedance (there's more thickness of metal in the ground net), and provide a slightly nearer sink for external fields (i.e., it improves shielding modestly).  Consider the case of a microstrip trace in an externally applied electric field: some field lines terminate on the trace, most sink to the ground beside it.  Well, if the ground were slightly higher up (on top of the dielectric, rather than buried under a little), slightly less field would terminate on the trace -- that is to say, less E-field couples to the trace, improving shielding.  A similar argument applies to external magnetic fields, blocked by the adjacent metal; the vulnerable loop area is already quite small (thanks to the shallow height of trace above inner ground, like the 7 mil dielectric as earlier), so this only reduces it modestly, but it definitely does provide a reduction, so may nonetheless prove worthwhile.

And if nothing else, I suspect it's more just a style thing, you know, it's this fancy converter with a shitload of bits, might as well guild the lily right?  No one's getting fired for pouring copper around the thing and taking a few extra hours stitching it, but managers aren't going to be happy if the thing is weeks to months behind schedule because it fails to produce the required ENOB / dynamic range / accuracy, or pass EMC (or both at the same time).

Tim

[davegravy]

Wow, thanks for this detailed reply! I have to re-read it (once or twice) and look up some of these concepts as they're a bit beyond my level but at least I know what to look for now.

One thing that remains unclear is how concerned with high frequency noise I need to be if in my application the input signal is audio frequencies. While I will be (over) sampling near the MHz range I'll be low pass filtering with an analog AAF, and using this ADC's integrated decimation filter (16x or 32x) to bring the data rate down to 25ksps or 50ksps. The stop band for the decimation filter alone is like 80dB attenuation IIRC.

I appreciate high frequency noise can alias back into the audio range but shouldn't these filters take care of it? Not that implementing this reference pcb layout scheme is a big burden for me, I'm just curious.

[T3sl4co1l]

Digital filters can't do anything if the signal looks like audio: see Fig. 21a for example,
https://www.analog.com/media/en/technical-documentation/data-sheets/251224fa.pdf
Read the whole section about aliasing and filtering in detail -- you need the analog filters (including supply filtering, to whatever extent PSRR doesn't handle it) to cut off well below Fs, because signals near Fs alias to audio.  And so on at the harmonics.

About PSRR (power supply rejection ratio), they don't even so much as mention it, which is peculiar (and frustrating; it seems ADCs rarely if ever do, at least I don't recall when I last saw one mention it).  They do at least give CMRR, which is stupendous (~ 150dB at filtering frequencies, and >80dB over the range shown).

Strange that they suggest a large ceramic cap for VREF bypass.  X7R is noticeably microphonic, meaning any motion of the board (flex, vibration, etc.) will be coupled into VREF itself; even if it's supplied from a stiff low-impedance source, there will be some residual coupling at high frequencies (opamps, regulators, references, etc. are all mostly inductive i.e. impedance increasing with frequency; the voltage is most accurate at low frequencies).  Easy fix, use an aluminum polymer type.  They're not microphonic, at least I don't think so.  (C0G ceramics are also an option, when the value doesn't need to be too big -- but they top out around 0.1uF, and are pricey up there!)

C0G are also an excellent choice for analog filters, with values in the 10s of nF being practical.  Otherwise, use PP or PPS film types.

Speaking of PSRR, your filter/gain/diff/whatever front end will be made of opamps that do have PSRR ratings (and won't be nearly as good as the ADC itself apparently is) -- make sure adequate filtering is present there, too!

Tim

[davegravy]

Digital filters can't do anything if the signal looks like audio: see Fig. 21a for example,
https://www.analog.com/media/en/technical-documentation/data-sheets/251224fa.pdf
Read the whole section about aliasing and filtering in detail -- you need the analog filters (including supply filtering, to whatever extent PSRR doesn't handle it) to cut off well below Fs, because signals near Fs alias to audio.  And so on at the harmonics.

Right but I'm trying to rationalize the concern with 10GHz coupling you mentioned in your first post given that even a 1st order AAF with a 20kHz cutoff will have massive attenuation up there. I suppose though that if 10GHz noise is on VREF for example, it's effectively bypassing the analog AAF, and as you say the digital filter is no help since the aliasing has already happened by that point.

Thanks for the tips about capacitor types, I'll make sure I try some of the options you listed.

[T3sl4co1l]

~GHz shouldn't be relevant for the system in question; likely it doesn't have much of any response beyond some 100s MHz.  (This is not necessarily the case: opamps can often have input rectification effects, causing demodulation of frequencies up there.  More and more often, these days, you see precision amp datasheets claiming EMI immunity -- typically done by adding RC filters on the chip itself, or something like that.  Very handy!)  I suppose I didn't make clear that, the ~10GHz stuff is simply a property of the structures -- vias spaced at such-and-such pitch creates a resonant or waveguide structure which is resonant up here.  Whether that is relevant to the system, is a different matter.

And, those passbands shouldn't be relevant, here, so that leaves the important part being the asymptotic (cutoff) behavior of those structures.  Which gets better roughly inversely to the frequency of interest.  So, for frequencies that are of interest (say 1s to 100s MHz), the structures themselves offer a good 40 to 80dB say, with respect to themselves -- which is still not to say, with respect to the system as a whole.

Finally, to be relevant to the system, there needs to be coupling between those structures, and any source of noise, internal or external.  The most important part is this one: the inner guard traces for example, are likely very weakly coupled to much of anything at all.  So that, not only do the frequent vias not do much, but the traces themselves probably don't do much if anything, either.  If you applied a signal to those traces and measured the response by themselves, you'd see something like the above description; meanwhile you'd see a tiny fraction of that coupled into, or out from, the surrounding circuit.

In contrast, if you consider ground traces or pours on the top layer, you'll get the same behavior again of course, but with potentially stronger coupling: as mentioned, the edge-wise coupling can be modest, like ~10% rather than -- I don't even know what; those ground traces might be a small fraction of a percent if they're just surrounded by planes anyways.  Or conversely, if traces run over/under them (without other planes inbetween), there can be much more direct coupling: again, if CPWG couples only ~10% to the same-layer ground, how much does it couple to the ground underneath?  90%, right.  So any disturbance that a trace runs over, is a huge liability as far as coupling noise in.  So the planes must be quiet and well bypassed, if there are any traces that are routed over them (i.e., on the bottom layer).

This was to answer your question about how frequent the vias are -- what characteristic that corresponds to, and whether it's important.  For which, there are likely more than needed.  But also, you'd need to model or test it to know for sure, and it probably doesn't hurt anything doing it like this, so one can argue from an abundance of caution that it's better with, than without.

Tim

[KT88]

A few comments:
-consider that 1LSB of 24 bits is less than 0.07ppm.
-3dB BW of this ADC is 34MHz - there will be still signals going through at >>100MHz.
-Any signal or noise reaching the input will deposit some amount of charge into the sample cap although attenuated according to the frequency roll-off of the input path. This will happen despite of a carefully designed AAF when allowed to bypass it and enter directly into the ADC input.
-Pretty much any pin of an ACD can act as an input for unwanted noise at certain frequencies. The internal structures are very small and always have some internal capacitive coupling. Shielding is usually applied to the most fragile structures such as the sample cap and the rest of the CAPDAC - but that is not perfect...
-The process nodes used for such devices are usually smaller than .5 microns with transit frequencies between 10 to 250GHz - this means that noise can even be amplified before interfering with the conversion...
This all means that it is practically impossible to over-engineer such a PCB...

Cheers

Andreas