Nah! The transistor doesn't care about Vdg being 7V, as long as its Source is tied to the Gate! It is a 60V device with a Vgs_th of 1.0 .. 2.5V, so a Vgs_th of 3.3V will open the channel all right in order to pass the 1..2mA pull-up Drain current.
Also, being in common Gate topology, it does not need any inversion at its input:
- When its input is logic-high Vgs == (Vdd-Vdd) = 0V, so the channel is closed and no Drain current flows; the output becomes +12V via the output pull-up resistor.
- When its input is logic-low Vgs == (Vdd-Vss) = (Vdd)V, so the channel opens and Drain current flows; the output becomes 0V via the logic output transistor of the level-shifter driver and the 5Ω transistor channel.
Actually, that circuit above, is a stripped-down version of the bi-direcrional level-shifter Philips proposed at their IIC protocol specification!
-George
EDIT: Clarifications and corrections.