When a bulk cap is recommended, it rarely matters where it is, so long as the local cap doesn't resonate with it (for which the ESR is indeed a good idea). They can be shared between devices, it might be the bulk cap on the supply regulator, etc. As long as it's reasonably nearby.
Datasheets make these recommendations on the assumption that the designer is both ignorant and forgetful; reminding them simply to put a capacitor nearby, is more likely to produce a successful outcome, than not saying anything at all, or of using a more complicated but accurate model of the device's PDN requirements.
The device in question, likely needs very little current indeed, and just needs relative peace and quiet to operate its analog innards. A bulk 10uF fed from literally anywhere on the board, is unlikely to help much in this regard, indeed I can quite quickly come up with counterexamples where it's likely to have no effect, or worsen things; maybe it can even cause it to oscillate, who knows.
The general truth is this: one cannot understand the device's supply from the 10uF down. It's a complete network of interaction, and everything matters.
As for 0.1's -- on a GND-VCC plane build, very few indeed might be needed. The inductance from pin to plane is dominant, and no amount of capacitors near those pins can fix the fact that the pins are inseparably there already. At best they can save some via inductance, but you can just as well double up vias if needed. Likewise any near-ish 0.1 looks like a low impedance plus some body, trace and via inductance, and these again can be reduced by using multiple vias in parallel.
The plane itself looks like a nearly ideal interconnect, with a small capacitance. (The capacitance itself is something to be careful with, as it can resonate in the ~100MHz range against some nH of stray inductance.) There is merely a small lateral spreading inductance, related to the distance between any given pairs of vias into the planes, on the order of log(distance) -- amounting to a few nH, even all the way across a board.
As long as you're using plane pairs, there's very little that 74HC, LVC and similar families, most CMOS devices (small ASICs, MCUs, FPGAs), and so on, will have troubles with. Sprinkle some bypass caps around the planes and be done with it. Can always put in more footprints as insurance, and a coax connector to measure actual supply ripple and verify that it's within tolerance.
Where local caps do the most good, is in 2-layer designs where only one net can be poured (GND), and even then it has to be poured on both sides and stitched with vias, religiously. There's no place for VCC to pour, so it must be routed point-to-point like any other signal. To maintain a low impedance, those routing traces need periodic capacitors to keep the impedance of the lumped-equivalent transmission line down.
That is, for a route with mostly equal distances between loads, a capacitor at each node gives an LC ladder circuit, with the L's being the trace inductance between caps -- ballpark 1nH/mm of trace length. The characteristic impedance is then Zo = sqrt(L/C), and for a linear (chain) routing topology, one or both ends of that route should be terminated with a bulk cap Cbulk >> Cbyp(tot) and ESR = Zo. A star or tree topology is also acceptable, given that every spoke/branch is similarly terminated at the end (the nodes will have low impedances, where the branches are acting in parallel, and bulk caps will be ineffective there).
A branch can also be series-terminated by using a series filter inductor L ~ Zo^2 * Cbulk, in parallel with a resistor Zo. This doesn't afford much actual filtering, and inductors are more expensive than capacitors, so it's rarely used. It does have the advantage that the network can be isolated somewhat from very low impedance elements (like low-ESR ceramic or polymer bulk caps, such as you'd use at the output of a regulator to achieve low ripple voltage).
You can design actual filter networks in the same way, using a relatively large series L and terminating it into a Cbulk + ESR, with ESR = Zo chosen the same way, this time using sqrt(Lfilt / Cbyp(tot)).
The meaning of impedance here, is this: consider a step change in a load. Maybe it goes from 0 to 100mA in a few nanoseconds or so. If it's nominal 3.3V supply, and ripple should be less than 5% of that, then peak voltage should be under 165mV, so the supply impedance should be under 1.65Ω. We could use 0.1uF bypass caps with a maximum mean length between them of about 27cm -- in practice we'd probably have loads every couple cm so this will be met easily. Note that 0.1's have an ESR around 50mΩ, so the Q factor will be quite high (~30?) if we do not employ a lossy bulk cap. If we have ten loads on this chain (Cbyp(tot) = 1uF), a Cbulk of say >= 3.3uF will do. If the mean distance between caps turns out to be 2cm, Zo will be closer to 0.447Ω so choose ESR = 0.5Ω give or take -- easily afforded with ceramic + resistor, or tantalum or polymer.
(Note that both tant and poly are available in wide ranges of C and ESR, the polys generally clustering in lower values, but there is significant overlap in available ESRs. Shop around, you'll find something that works.)
Electrolytic is less preferable, because ESR increases considerably at low temperature, or past end of life, and the capacitance tolerance is awful. A good strategy then is using more than needed, so that its Cbulk hardly matters ("Cbulk >> Cbyp" as in 100 times or more) and dominates other reactances on the net, and so also its ESR dominates (which can be chosen say 2-3x lower than ideal, for this reason).
Tim
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