Author Topic: VHDL - Link pins from different entities  (Read 969 times)

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Offline soFPGTopic starter

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VHDL - Link pins from different entities
« on: May 06, 2018, 12:41:21 pm »
I am trying to copy a simple existing CPU inside a microcontroller.

For initial testing purposes I tried to set the program counter to start value 0x000 and hoping for a change at the "instruction-bus", these are my two VHDL-entities involved:

Code: [Select]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MDT90P01 is

port (

pc: out std_logic_vector(8 downto 0);
c0: in std_logic;
w_reg_top: in std_logic_vector(3 downto 0);

instruction: in std_logic_vector(10 downto 0)
);

end MDT90P01;

architecture Behavioral of MDT90P01 is

begin
process(c0)
begin

if(falling_edge(c0)) then
pc <= "000000000";
end if;

end process;

end Behavioral;

Code: [Select]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.all; 

entity Instruction_Memory is

port (

pc: in std_logic_vector(8 downto 0);
instruction: out std_logic_vector(10 downto 0);
c0: in std_logic

);

end Instruction_Memory;

architecture Behavioral of Instruction_Memory is

type ROM_type is array (0 to 511) of std_logic_vector(10 downto 0);
constant rom_data: ROM_type:= (
"10010000110",
"10010000110",
(others=>'0')
);
 
begin
process(c0)
begin

if(rising_edge(c0)) then
instruction <= rom_data(to_integer(unsigned(pc)));
end if;

end process;

end Behavioral;

But ModelSim-Altera only shows me this, I expected "instruction" to be "10010000110" but it isn't - why?

« Last Edit: May 06, 2018, 12:45:59 pm by soFPG »
 

Offline rstofer

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Re: VHDL - Link pins from different entities
« Reply #1 on: May 06, 2018, 02:01:59 pm »
I don't see a 'top' module where you tie the signals together.  Usually this module will just define the various signals and connect them between lower level entities.  You may have such a module and didn't post it.

'pc'' is declared as an output in MDT90P01 and as an input in InstructionMemory but there doesn't seem to be anything tying the ports together.
 
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Offline soFPGTopic starter

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Re: VHDL - Link pins from different entities
« Reply #2 on: May 06, 2018, 02:10:51 pm »
Quote
'pc'' is declared as an output in MDT90P01 and as an input in InstructionMemory but there doesn't seem to be anything tying the ports together.
MDT90P01 is the Top-Level Entity. I am new to VHDL and unaware of that different entities need to be tied together besides equal port names.

I added this:

Code: [Select]
architecture Behavioral of MDT90P01 is

signal pc_int : unsigned(8 downto 0);

begin

instr_inst: entity MDT90P01.Instruction_Memory
port map(pc => pc, instruction <= instruction);

process(c0)
begin

if(falling_edge(c0)) then
pc <= pc_int;
pc_int <= pc_int + 1;
end if;

end process;

end Behavioral;

but I get:

Quote
Error (10594): VHDL Selected Name error at MDT90P01.vhd(24): object "Instruction_Memory" isn't declared in scope "MDT90P01"
 

Offline rstofer

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Re: VHDL - Link pins from different entities
« Reply #3 on: May 06, 2018, 05:41:57 pm »
I know I'm going to screw this up...

Assuming your entities are in separate files in your workspace:

Code: [Select]
library stuff...

entity myproject is
Port (
  clk : in std_logic;
);
end myproject;

architecture Behavioral of my project is

signal pc : std_logic_vector(8 downto 0);
signal c0 : std_logic;
signal instruction: std_logic_vector(10 downto 0);
signal w_reg_top: std_logic_vector(3 downto 0) := (others => '0');

begin

c0 <= clk; -- for example

inst_PC: entity work.MDT90P01 Port Map (
  pc => pc, -- hook up the wires
  c0 => c0,
  w_reg_top => w_reg_top,
  instruction => instruction
);

inst_InstMemory : entity work.Instruction_Memory Port Map (
pc => pc, -- hook up the wires
instruction => instruction
);

end Behavioral;


Something like that...

ETA:  I had left out a couple of details...
« Last Edit: May 06, 2018, 06:53:18 pm by rstofer »
 


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