Electronics > Beginners
Voltage Follower
KW:
Hello everyone...
I just configured a simple voltage follower as shown in the figure below. I use a model of TL-071 op-amp for my setup. The VCC and VDD is connected to a +15V and -15V power supply separately. In the meanwhile, Vref is connected to a 1V power supply.
At the beginning, all of three power supplies (VCC, VDD, Vref) are turned off. When the VCC is turned on and the others power supplies are in off condition, a high voltage, Vout is coming out (around +14.5V). But when the VDD is turned on, the Vout will back to ~0V.
Does anyone know why the high voltage only comes out at Vout when the VCC is turned on first?
Please comment and give some suggestions to minimize the voltage at the Vout when the VCC is turned on first.
Thanks.
Nerull:
You have a component with one connection, to +15V. I'm not sure how you expect it to produce any other voltage on the output.
Do you find components often function when only connected to power and not ground?
KW:
Thank you for your replying.
In my case, all of three power supplies (VCC, VDD, Vref) at the figure are connected a common ground.
In this experiment, I expected when the VCC (+15V) power supply is turned on first will result a 0V at Vout but this doesn't happen until the VDD (-15V) is turned on.
A huge voltage difference occurs at the Vout at different switching sequence:
1. VCC (+15V) is turned on first later on by VDD (-15V) - Vout = ~ +14.5V
2. VDD (-15V) is turned on first later on by VCC (+15V) - Vout = ~ -1.0V
Ian.M:
You've got a power and signal sequencing problem. Generally, both supply rails of a dual supply OPAMP should always have their voltage applied (and removed) at the same time. Also, no signals should be applied unless the operating voltages on the supply rails are present and stable.
For specific OPAMPs and application circuits it may be permissible to apply signals before power. e.g. if the absolute maximum input voltage range extends considerably beyond the rails, or if the input circuit has enough resistance to limit the input current enough to prevent damage. See OPAMP datasheet + any available manufacturer's application guides for that OPAMP, and consider carefully if the specified permissible input voltage range could be violated transiently during powerup or powerdown.
If you use mechanical or independent supply rail switching, or there is any other way one rail may become disconnected, even momentarily, it may be helpful to put reversed biassed diodes between both rails and ground so neither rail can be dragged past ground when it isn't powered. It will still misbehave, but usually less severely than if a rail is totally disconnected and floating.
I would also recommend 10K resistors in series with each input (i.e. one between Vref and in+ and the other in the feedback loop, so the input bias currents for both in+ and in+ cause similar voltage drops).
CatalinaWOW:
There is no generic answer to your question. The result lies in the details of the op amp implementation. Not just the schematic of the op amp internals, but also all of the parasitic junctions that occur due to the fab process. When specified voltages are applied the parasitic junctions are all properly biased to prevent any impact on operation and the circuit will work as designed.
In your test case there is a complex (meaning there are multiple signal paths, some of which may involve diodes or transistors), probably high impedance path to ground through the 1.0 volt reference circuit. And then whichever supply you turn on. Your results are not surprising, but as others have said, might be totally different with another type of op amp, and possibly different with another sample of the same type.
If your application requires the output to be maintained below a certain level you must control power supply sequencing, and possibly clamp the inputs and output by some means until the supplies are known to be up and stable. Power supply sequencing is itself a fairly large subject and can include limits on how long one supply can be up before the other, and ramp rates on the turn on.
This is one of those details often skipped in university classes and intro textbooks that causes young engineers much stress in the real world.
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