PCB stacking for high speed lines - help understand when PWR reference plane is

[jmf11]

Hello,

I'm an hobbyist designing an stm32H7 + USB 2.0 HS + 49MHz clocks project for Audio. This seems at the edge of real high speed constraints, but still an opportunity to learn (and avoid possible problems). I will use a 4 layers PCB and procrastinate about the stacking between:
- classic SIG/GND/PWR/SIG
- could be better for high speed lines SIG+PWR/GND/GND/SIG+PWR (ex from https://resources.altium.com/fr/p/two-alternative-4-layer-pcb-stackups-50-ohms-impedance).

As my design is sort of Audio System On Module, it has connectors all around the board to expose many signals from the MCU. SIG/GND/PWR/SIG seems the best for high speed signals integrity perspective, but I don't get a good strategy to distribute power to the different chips whithout creating lot of constraints for the routing of sensitive lines from the MCU to side connectors. A PWR plane would help there for the newbie I'm.

However here and there I see that a PWR plane is also fine for high speed lines routing:
- https://electronics.stackexchange.com/questions/41470/the-best-stack-up-possible-with-a-four-layer-pcb
- https://electronics.stackexchange.com/questions/663105/is-pwr-plane-acceptable-as-return-path-for-high-speed-signals-instead-of-gnd

I would like to understand when using PWR as Reference plane is OK, and when it is not. What are the uses cases where IG+PWR/GND/GND/SIG+PWR is relevant and SIG/GND/PWR/SIG is not.

Help welcomed to get me over the bump and moving again.

Best regards,

JMF

[madires]

Please search YouTube for 'Rick Hartley' and you'll get plenty of answers.

[jmf11]

Thanks for the hint, I will watch some of those. That one for example ?

JMF

[T3sl4co1l]

Microstrip traces over ground plane makes a transmission line, a two-port element.  Within the transmission line, the signal couples to the ground and vice versa.  When the plane is the reference place, the coupling is trivial (there's no induced interference from that which is defined as zero).  When the plane is a supply, there may be noise on it, relative to the actual reference plane, and some amount of that will be coupled into the signal trace.

Whether that's a problem, depends on the application, signaling and so on.

For a typical example, where the power plane is wide, closely coupled to the ground plane (e.g. bypass capacitors scattered around evenly), low ripple (a typical digital design might have 10s mV of ripple, if that), and LVCMOS digital signaling is in use, the signal level (3.3V say) so thoroughly exceeds the plane's ripple that it doesn't matter, and it's as good as ground for signal purposes.

The same might not be true of an analog signal, or RF.

Note that you can also do a pseudo 3-layer layout, i.e. preferring top routing where possible, and keeping bottom routes short (jumpers at bus crossings).  This may take up more board area (forces a lower component density) so it depends.

Tim