As promised a narrative of a circuit design, something I'm still working on.
As part of something I'm designing (for myself as a hobby project) I have a need to measure the timing of a digital signal to a greater resolution than my system clock will allow. The system clock is 10MHz but I want to measure the time between two subsequent input pulses to better than the 100ns resolution that this clock allows.
What I'm measuring is the time between successive 1 Pulse Per Second (PPS) pulses from a GPS timing receiver. The timing receiver in question itself uses a 12.504 MHz and can only select one of those clock edges to output the PPS signal on, this means that the timing of the physical output signal only has a resolution of 39.98ns. However, internally it can calculate the timing of that signal to higher precision. The receiver has an accuracy of around ±15ns and a quantization error of ±20 ns from the clock edge selection. It will output, as serial data, the difference between when the PPS is physically output and when it should have ideally been output. This correction factor is available as a single precision floating point number, which is good enough that we can presume that it doesn't dilute the precision avalable internally.
My objective is to measure the actual transition of the PPS signal with sufficient precision and accuracy that I minimise how much I dilute the innate accuracy of the GPS timing modules. Obviously sampling at my 100ns clock would result in terrible dilution of the precision available from the GPS timing receiver. So I need a way of measuring the signal with greater precision and finer resolution.
Now, I had two choices here. Stick with the digital domain or switch to the analogue domain.
Sticking with the digital domain would be simple, but would require using a much faster clock and much faster digital electronics to be able to count at a rate fast enough to capture meaningful resolution. Any compromise in clock speed will reduce the precision available to me. My current choice of digital circuitry is a Lattice MachXO2 FPGA, picked becuase it's a cheap part, available in QFN packaging so doesn't require an exotic PCB and a cheap breakout board is available. These come with an integral PLL that I could use to multiply up my 10MHz system clock. The XO2 will run a 16 bit counter at 324 MHz and a 64 bit counter at 161 MHz, timing for a 32 bit counter isn't offered in the datasheet. A guesstimate says that I could run a 32 bit counter at 200-250MHz giving me a timing resolution of 4 to 5ns. That's an unattractive resolution compared to the inate uncertainty of ±15ns of the timing receiver, adding something like 33% more uncertainty.
There are several techniques in the analogue domain for 'time interpolation' that can be used to measure the difference between when the PPS pulse arives and the next clock edge available in my digital domain, using this as a vernier indication against the main clock. This is where previously having spent time pouring over other people's designs comes in. From looking at and studying the designs for the HP 3458A multimeter, several of HP's scopes, some of HP's timer/counters and Tektronix scopes I'm aware of several possible designs for time interpolators.
There's a fantastic method using a "Triggered Phase-Locked Oscillator" and digital vernier interpolation used in the HP 5370A Universal Time Interval Counter. It's capable of producing 20ps single shot time resolution but sadly requires the use of custom hybrid circuits to make the "Triggered Phase-Locked Oscillator". So that technique is out.
Most of the other time interpolation methods are variants on the dual slope integrator. They charge a capacitor from a constant current source for the duration of the pulse to be measured, and then discharge the capacitor uisng a much weaker constant current source. This has the effect of stretching the input pulse by the ratio between the two current sources. It's a fairly simple thing to count clock pulses between when the integrator capacitor starts discharging and when it reaches a quiescent 'between measurements' condition using ones slow clock, a comparator, a counter and some sort of state machine to manage the whole process.
How good you can get this dual slope technique to work is a combination of two things, how high you can push the ratio between the two current sources and how stable the circuit is against temperature induced drift and all the other things that cause an analogue circuit to drift over time. Getting a ratio of 1:1000 shouldn't be too difficult. Making reasonably stable current sources in the region of 1uA and 1mA is quite practicable.
So this is the route I went down. The schematic for the current state of play is below. It has got to the "checking it out in LTSpice" stage. It hasn't yet met the real test, which is to prototype it and see how the whole design holds up in the real world. I'm happy with it so far, but I'm not holding this out as an example of good design just as an example of what the design process looks like and some of the decisions that have gone into it. I'm sure the professionals can pick plenty of holes in this particular circuit, when it comes to electronics I am only a humble hobbist after all.
What you're looking at is a circuit designed to take an input pulse that is 100-200ns long, and output a pulse that is approximately 1500 times longer at 150 to 300 us. The length of the output pulse is directly proportional to the length of the input pulse ± some constant. Both the ratio of proportionality and the constant offset will drift with time and temperature. With my 10MHz, 100ns, system clock that gives me 100ns/1500 = 67ps theoretical resolution.
Linearity of the pulse stretcher, as designed, for short pulses is terrible, moreover, producing short calibration pulses for it would be impractical. If we tried to measure a 1ns pulse directly we'd get rubbish results, instead the pulse to be measured is used along with the system clock to gate a flip flop in such a way that the pulse fed to the pulse stretcher runs from the rising edge of the input pulse from the GPS receiver to the second rising edge of the system clock following, so we effectively add 100ns to every pulse that we measure - we can get rid of that in software further down the chain.

(That's a bit difficult to read. If you open the image in it's own window it's a lot better.)
The whole thing is built out of quite standard building blocks. There are current sources/sinks, there's a differential amplifier doing service as a threshold detector and level shifter. There's a differential pair operating as a current switch. There's an integrating capacitor, a clamping diode. The slope amplifer and comparator on the output are quite conventional and are probably underdesigned at the moment. Once the first prototype is built up I'll want to take a careful look at the anti-windup provisions on the op amp, its gain and will possibly add some hysteresis to the comparator - it works fine in simulation but I doubt it will in real life without hysteresis.
There's a classic theory <=> practice isssue here - the simulation has no power supply bypassing. The op amp and the comparator will both need nearby supply bypassing, especially the comparator. Fast comparators tend to chuck at lot of current pulses into the rails and can become horribly unstable without adequate bypassing.
I chose 3mA nominal as the integrator charge current. That's enough to be quick, not so much that the current source and current switch will suffer much from drift from self-heating. I chose a nominal 1uA for the discharge current, and ended up with around 1.2uA. This was picked on the basis that I didn't think I could get away with a lower current. I also chose to simplify the design by not switching the discharge current. Logically one would, but with the high charge/discharge ratio it doesn't stop the integrator from charging over a useful range. Adding the necessary level shifting and switching would have complicated the design to no practical end. The small constant discharge current just drops out as a constant when you do the calibration described below.
The diode clamp that holds the integrating capacitor at its quiescent, between measurements, voltage is constructed with a diode wired JFET. With the low 1.2uA discharge current it was important that the contribution from leakage current from the clamping diode was minimal. A diode wired 2N3904 would probably work just as well in a low voltage circuit like this (the possible reverse bias voltage isn't enough to cause breakdown problems) but I
like JFETs.
I expect both current sources to drift. Dual slope integrators automatically deal with many of the non-idealities of the real world, their biggest contribution in this regard is that although the integrating capacitor may drift, it's the raio between charge and discharge times that matters, not absolute voltage reached, so any drift automatically cancels out. Drift in the current sources will be dealt with by measuring a 100ns and a 200ns calibration pulses immediately after taking the actual measurement - a circuit isn't going to drift much over a few milliseconds. Having two known input pulse widths and two measured output pulse widths one can easily calculate the constants for a y = mx + c style equation where x is input pulse length and y is output pulse length.
Many decisions were quite arbitrary. The op amp and comparator choosen where picked on the basis of working with ±3.3V rails, being fast enough and not too expensive (there are no really cheap, fast comparators). They could easily change with little effect on the basic design.
Taking the simulated timings, sticking them into a spreadsheet, quantizing the results to a 100ns clock (including the 100ns/200ns calibration) gives a worst case error of 0.12% against simulated input pulses at 100ns, 101ns, 102ns,..., 200ns. How that holds up in the real world remains to be seen and will probably stretch the limits of my available signal sources - it might even be an excuse to buy some more test gear.
So, that's an isolated part of a larger system with some of the thinking that went into the design. We've covered where the basic circuits ideas were borrowed from. We've covered some design decisions forced on us by real world component/circuit behaviour. I'm aware that I've only scratched the surface and I've almost certainly glossed over some decisions I made. But as a snapshot of the design process from "here's the problem" to "here we are ready to do some physical prototyping" I hope it's useful.