EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: dsharp02 on July 04, 2017, 05:48:32 am
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I've been playing around with EasyEDA, and I like it a lot. However my schematics are a mess. What can I do to clean things up?
I've attached a copy of one of my schematics for reference.
Thanks,
Dave
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what in particular makes you think its a mess.
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One step would be to use the GND and VCC simbols instead of drawing the power wires.
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All power lines have to be changed to power symbols, that's for sure.
I also use broken lines with labels on each end for lines that are too long and go all over the place. Example: https://github.com/ataradov/free-dap/blob/master/hardware/d11_usb_mini.pdf
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That's actually not bad. The rules I hate to see violated senselessly are those that say: Power at the top, ground at the bottom, signals flowing from left to right. But you respected those rules. As RoGeorge points out, you could use symbols for power and ground, especially where you feed them into the ICs, to eliminate a bit of clutter.
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That's actually not bad. The rules I hate to see violated senselessly are those that say: Power at the top, ground at the bottom, signals flowing from left to right. But you respected those rules. As RoGeorge points out, you could use symbols for power and ground, especially where you feed them into the ICs, to eliminate a bit of clutter.
Yep it's neat enough but as each has said assign the GND and VCC nets and use net labels for connectivity that the package should sort out for you. You should be able to make the IC power pins invisible and the package just know that need connectivity when you come to the PCB layout.
The 75440 for example could have those 4 GND pins linked at the IC and either just one connection to GND or add a power net connection signifier and let the package sort it out. For this to work seamlessly the IC pin need have exactly the same name as the power net.
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Generally not bad. One rule you haven't totally followed is to make the signal flow dominant. Changing supplies to bus type connections as others have suggested will go a long ways toward this. Move your input connectors to the far left of the page, and label the actual signal pin (pin 2) as signal.
Another minor changes would be to come up with a short name for the input connector type. The mind equates area with importance and this name occupies space totally out of proportion to its actual importance.
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I've just spotted the wires crossing and joining on the diodes at the right hand side of the schematic, that's a definite No! Wires should either cross, or join (T-junction style), but never join on a cross.
Nip the habit before it sticks. ;)
EDIT: An excellent example of why you don't do it is the misplaced connecting dot on the wire going to U1, pin 13. Do that on a cross and you'll be in a mess.
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You have duplicated the power and ground connections on the op amps. I guess using power and ground symbols would remove a bit of clutter but, overall, I like it. The power rails are in the right place, the logical flow is left to right, I don't have any heartburn with the dot connections but I do have a problem with the abandoned dot U1-13.
I don't really have a problem with the diode connections. It clearly shows the intent.
Overall, I like it! It's better than most of mine!
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If we are going to nitpick, I prefer putting stuff like pullup resistors, decoupling capacitors, etc. close to the device they are pulling up for. Examples here would be C1 and C2, R4 and R5.
Also, I like when people group stuff. Net lables should be used sparingly - none of this "IC pin to netlabel stuff". I myself am still undecided if I like conectors to be the start of the "signal" or send the signal from the connector straight to a netlabel, and then start the netlabel somewhere else.
I'll upload some pictures later when I have time.
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I've just spotted the wires crossing and joining on the diodes at the right hand side of the schematic, that's a definite No! Wires should either cross, or join (T-junction style), but never join on a cross.
I din't personally see anything wring with this. Plus in this case the intent is very clear, and doing things otherwise will create more mess.
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Your schematic is actually very decent. :-+
Other posters have already made their (good) comments, I won't repeat them.
Thus I'll only add that some times in very tightly drawn schematics, when one has several identical devices clustered together, it helps to do a global description like:
"D1 thru D8: 1N4007"
instead of listing each device:
"D1 1N4007"
"D2 1N4007"
"D3 1N4007"
and so on............
It may not matter on a short name like 1N4007, but nowadays some components have humongous part numbers, and it adds to visual clutter quickly.
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I've just spotted the wires crossing and joining on the diodes at the right hand side of the schematic, that's a definite No! Wires should either cross, or join (T-junction style), but never join on a cross.
I din't personally see anything wring with this. Plus in this case the intent is very clear, and doing things otherwise will create more mess.
I agree with "definite No!" I've seen schematics where crossed lines are sometimes connected and sometimes not. Or where it's hard to read whether there's a connection dot on the crossed lines. So I think it's good practice to never have crossed lines that are connected. I don't find this to be messy at all.
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General points...
Signal flow left to right and top to bottom, except for feedback paths.
Signals connected together should have a line between them; if you don't, how can you be sure that you have spotted everything on that net?
Many common "design patterns" (e.g. op amp integrator, or op amp current source) are traditionally drawn in a certain way. If you have such a block, draw it in the conventional way.
Circuit diagrams are read far more often than they are written, and are read by people that don't know the circuit in intimate detail. Draw whatever is necessary to allow other people to understand the circuit's intended operation.
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Thank you all for the advice. I've tried to follow everyone's suggestions, and I have attached the result. If you still see room for improviement, let me know.
Thanks,
Dave
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I like it. To me this is much more readable than the first version.
One note though: if you export to PDF, make sure that it is searchable. Those lose ends turn into total nightmare on a multi-sheet schematic without ability to search.
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I'm far from an expert but on a simple schematic like this breaking everything into sub sections is making things less clear for me, I like to see how the signal flows without having to make mental leaps (I could be in the minority).
I'm loving the thread though, some great ideas.
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Thank you all for the advice. I've tried to follow everyone's suggestions, and I have attached the result. If you still see room for improviement, let me know.
There is, ~1/2 way between your two versions.
For this design there is little need to break the schematic into each of the functional blocks, for higher density and more complex multi-sheet designs it's a good idea.
Firstly get rid of the multiple VCC paths to each part of the IC, sure show it on one part, you pick which.
You've got the other VCC's and Gnd's right. :-+
Either C1 or C2 can be omitted, you don't need that much capacitance on each VCC pin....why 100uF ? Misprint ?
If one is a pull-up only then there is little need for capacitance on it.
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Nice
Flip R3 vertically.
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There is, ~1/2 way between your two versions.
For this design there is little need to break the schematic into each of the functional blocks, for higher density and more complex multi-sheet designs it's a good idea.
Firstly get rid of the multiple VCC paths to each part of the IC, sure show it on one part, you pick which.
I tried connecting VCC and GND only on op-amp 1.1 but the PCB software seemed to have issues with it. I ended up with wierd issues where the GND pin of the LM324 wasn't connected to anything. So my work-around was to connect every op-amp to both VCC and GND.
Either C1 or C2 can be omitted, you don't need that much capacitance on each VCC pin....why 100uF ? Misprint ?
If one is a pull-up only then there is little need for capacitance on it.
Pins 8 and 16 provide the power for the h-bridge on left and right side of the chip respectively, so I put in caps for those pins, not for the pull-ups. As for why 100uF, it was just a number pulled out of thin air. :D I used the same amount for C3 to minimize the number of different parts.
Thanks,
Dave
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There is, ~1/2 way between your two versions.
For this design there is little need to break the schematic into each of the functional blocks, for higher density and more complex multi-sheet designs it's a good idea.
Firstly get rid of the multiple VCC paths to each part of the IC, sure show it on one part, you pick which.
I tried connecting VCC and GND only on op-amp 1.1 but the PCB software seemed to have issues with it. I ended up with wierd issues where the GND pin of the LM324 wasn't connected to anything. So my work-around was to connect every op-amp to both VCC and GND.
Gotcha.
If there's any discrepancies in the net names it'll probably spit the dummy, recheck assignments and names.
You can get caught out with these, some devices call their power supply VCC and other VDD. To reduce the chance of error I how rename all power nets to +5, +12 or whatever.
This is a pretty basic requirement of PCB software and I after checking the IC pin power assignments are correct make the power connections to the IC invisible. (not shown)
It makes for a much tidier layout.
I'm no real expert, much of what I've learnt has been through some little experience and is primarily based on mimicking the beautiful schematics of yesteryear. Grab some service manuals of test equipment and study the layout formats used in those schematic.
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Good job.
You are on a tough boundary as far as breaking this thing into subsections as you have in your second effort. As a couple have commented the circuit is not complex enough to normally warrant this. But it eliminated a lot of criss-crossing wires which is a big positive.
Some schematics can have a lot of components with very little crossing topology. Others turn to spaghetti with just a few. There is no single rule for them all.
At this point, pick what works best for you (and the rest of your team if you are working in a group situation).
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Can't the grid in the background be turned off?
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i like that you are using the "common" symbol rather than the ground or earth symbol.
Funny everyone here is saying "ground".
Into audio engineering, this stuff counts.
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Thank you all for the advice. I've tried to follow everyone's suggestions, and I have attached the result. If you still see room for improviement, let me know.
Without connecting lines, how do I know I've spotted everything connected to IC3 pin 6? Arguably it is possible on this small diagram, but it becomes impossible on larger diagrams.
Consider scalability of your approach; for larger circuits, have hierarchical diagrams. Each diagram then shows a separate conceptual subsystem, e.g. analogue input, motor driver, controller, and there is a higher level showing just the subsystems and their interconnections. Analogy: in software you have a main() function which calls other functions, such as the pseudocode
controlMotor() {
setPoint = readVoltage1();
position = readVoltage2();
correction = pid(setPoint, position);
pokeMotor(correction);
}
int readVoltage1() {
...
}
int pid(int sp, int p) {
...
}
etc
How does the grid aid understanding? It doesn't, so delete it.
The schematic serves two purposes: to help engineers and technicians, and to generate a netlist. Sometimes those purposes conflict, e.g. with having "too many" power connections. Where necessary, have multiple different names, e.g. AGND and DGND.
"Generic" decouplers, especially for digital ICs should be grouped away in a corner, since they don't aid understanding and during layout are "sprinkled" across the PCB. OTOH, decoupling arrangements for analogue ICs are often shown on the schematic next to the relevant IC.
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Without connecting lines, how do I know I've spotted everything connected to IC3 pin 6? Arguably it is possible on this small diagram, but it becomes impossible on larger diagrams.
I don't make schematics that take more than a few pages, but for work I have to read schematics that are 20+ pages from time to time. And most of them drawn in that "disconnected" style. And I personally prefer it.
And they all come from different authors, so there is some sort of agreement there.
With search you can find all the places signal is mentioned, if you need to know this information. But in many cases you don't really. Especially for things like 144-pin FPGAs, or 100-pin MCUs.
And doing point-to-point lines for MCU + SDRAM is virtually impossible.
Some schematic capture software can actually put page numbers where this signal is used in parenthesis after the signal name. This helps as well.
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Without connecting lines, how do I know I've spotted everything connected to IC3 pin 6? Arguably it is possible on this small diagram, but it becomes impossible on larger diagrams.
With search you can find all the places signal is mentioned, if you need to know this information. But in many cases you don't really. Especially for things like 144-pin FPGAs, or 100-pin MCUs.
You make presumptions that are often not valid - particularly for large designs, designs that are important for more than a short time, or for designs produced by a different company.
How do you search a jpg?
How do you search a paper document?
How do you search an Altium (etc) schematic where you don't possess Altium?
And doing point-to-point lines for MCU + SDRAM is virtually impossible.
No, it is entirely possible and easy - as has been demonstrated in professional designs since the 1970s (and earlier)!
What you do is have each address line (data/control) coming from a pin and entering an address bus (data/control). You then route the bus around the diagram. Typically the bus is shown as a wider line.
The first example that comes to hand is shown below: a small snippet of one diagram for a Tek 2445 scope.
Some schematic capture software can actually put page numbers where this signal is used in parenthesis after the signal name. This helps as well.
That can help a bit, but isn't sufficient.
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Your schematic is actually very decent. :-+
Other posters have already made their (good) comments, I won't repeat them.
Thus I'll only add that some times in very tightly drawn schematics, when one has several identical devices clustered together, it helps to do a global description like:
"D1 thru D8: 1N4007"
instead of listing each device:
"D1 1N4007"
"D2 1N4007"
"D3 1N4007"
and so on............
It may not matter on a short name like 1N4007, but nowadays some components have humongous part numbers, and it adds to visual clutter quickly.
I don't do this. Instead I'll group D1 through D8 do that they're all bunched up together with obvious gaps to the nearest components. The Ref Des is left by each component, but the value fields (all 1N4007) are stacked on top of each other, with every one visible.
This way, if one of the values is wrong, you can still see it. Only if they're all the same can you read the value.
Other rules of mine:
Pull up/down comps are always vertical.
Use the same spacing across the entire schematic. If your symbol pins are on a 0.1" pitch, your entire grid should be on that pitch. Associated wires (eg all wires on a peripheral bus, data, r/w, cs) should be spaced 0.1" apart. Use a gap of at least 0.2" for unassociated wires.
Never change net names as your signals traverse a Hierarchy, unless it can not be avoided (multiple reuse of H-Blocks). In this case if the signal name outside of the H-Block is FRED and the H-block name is BLOCK, then the signal name inside the H-block is BLOCK_n_FRED. This will be controversial as it will slow your schematic capture, but it will pay you back ten fold when you try to debug.
Never forget that schematics are the EE's art. They should be beautiful. You should look at a sheet and instantly know what is going on. Not with every component, but you should see purpose and dataflow at a glance.
Never be scared to create a new schematic body and move the pins around to achieve simplicity.
On really big schematics, come up with a net naming convention before you start.
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Dont break schematic into very small sections, like second example. Dont leave it as very big sections, like first example. Also current goes mostly from top to bottom, and from left to right. Except feedback.
And change to IEC symbols for passive, keep using ANSI for active. Trust me, schematics look 100 better that way.
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Never forget that schematics are the EE's art. They should be beautiful. You should look at a sheet and instantly know what is going on. Not with every component, but you should see purpose and dataflow at a glance.
Very true; my emphasis added.
Anything that impedes seeing those thing is unwelcome.
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Oh no. Oversized PNGs! another one of my pet peeves. It wastes Dave's bandwidth.
The file sizes of the images posted in this thread are much too large!
dsharp02, tggzzz,
How did you make those files so big?
I've converted the colour one to 8-bit indexed and the monochrome one to 4-bit with no transparency. Now look at how much smaller they are! There's no need for low compression ratio 32-bit colour images for schematics.
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Never forget that schematics are the EE's art. They should be beautiful. You should look at a sheet and instantly know what is going on. Not with every component, but you should see purpose and dataflow at a glance.
Very true; my emphasis added.
I always say that a schematic is an electrical roadmap
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Whats the point of a Schematic.. Its to convey information to the people that need to read it.
If the schematic is just a sketch on my notebook, for me to remember to do something, then if its a bit rough, its not important..
If the schematic is somethign that i'm going to use by myself, then there are a lot of assumptions that i can make and i can be a bit less careful with it.
When i have to share it with others, then i really have to be careful.
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Your 2nd revision is definitely an improvement from the 1rst (although, the 1rst wasn't so terrible in my opinion). In the 2nd version, you might have gone a bit overboard with the segmentation blocks. In general, I try to keep my analog circuits more continuous, so I can see at a glance the purpose of the circuit and, usually, the topology of the implementation. But for digital circuits (i.e. IC-to-IC serial connections) I almost exclusively use net labels. Attached are some examples. Everyone does have style differences, so it's difficult to quantitatively say one style is superior. Of course there are general rules of thumb and conventions (as others have already explained). Following an employer's conventions could be one of the most important considerations.
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Yes, this is a much better example of what I was trying to covey with words. Digital -> net labels, analog or standard circuits -> connected.
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I was about to say, "your schematic is already better than many others I've seen; for a start, it actually connects the parts together"... and then I saw the second "improved" version. :palm:
A schematic is not a bunch of parts with netlist labels. Count me as one of those who liked your first version more. I've read a lot of laptop schematics and they're all scattered, barely-connected blocks, not because it's better, but because it's easier and lazy. In fact I believe those are automatically generated "schematics" from the netlist. IMHO if you need to use Ctrl+F (which does NOT work on an image) to see where some signal goes, you've failed.
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I don't see how buses help you find all the places signal is used. Buses are basically the same as net labels, except you don't need to run additional thick lines everywhere.
It is not lazy, it is practical for large digital circuits. I don't remember when was the last time I actually had to look at a printout of a schematic for normal work.
I do printouts for reviews, but there I typically want to put marks next to things I've checked, so PDFs are not very practical for that.
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There are times when the schematic symbol of an IC just won't allow for neatness and sometimes it's good to create your own, power pins top and bottom and I/O's left and right. Some EDA package have a # of symbols for each IC but when they don't and you still wish to show connectivity and signal path flow the solution is to build your own.
It's good to see a well laid out schematic, it serves as a record of the various calcs made in determining the values used of individual components. Sure scribble down a concept but take the time to draw a decent schematic too.
The more you do, the faster and more polished you become.
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Oh no. Oversized PNGs! another one of my pet peeves.
How did you make those files so big?
I just did a screen cap and cropped it to size. My apologies for not taking the time to shrink them down a bit, I'm on a fast connection and didn't think about the impact to bandwidth. In the future I'll try to be more careful with my attachments.
Dave
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I don't see how buses help you find all the places signal is used. Buses are basically the same as net labels, except you don't need to run additional thick lines everywhere.
It is not lazy, it is practical for large digital circuits. I don't remember when was the last time I actually had to look at a printout of a schematic for normal work.
I do printouts for reviews, but there I typically want to put marks next to things I've checked, so PDFs are not very practical for that.
I'm sorry, I could not disagree more. A schematic has two functions:
1/ Graphical generation of the netlist.
2/ To convey information.
You've met the criteria of 1/, but this type of schematic utterly fails to convey information. Someone not familiar with the design will struggle.
It is poor practice to force engineers to use CTRL F to hunt down each and every connection, then hold that connectivity in their heads whilst they track down the next net.
Using net names to link blocks everywhere IS just laziness. I don't agree it's about being practical, both methods can be done, so both methods are practical. Sure your method is faster to draw and sure, you will be able to follow it, so why bother putting the extra effort in?
Drawing the connectivity not only makes debug easier, it makes review easier too. I believe it makes design more rigorous too, working graphically gives you a perspective you don't get otherwise. So whilst it may take longer to draw connectivity, you will have a better schematic and that will save time in the years that follow capture. Surely that is more practical than banging out any old rubbish as fast a possible?
Don't get me wrong, I have tried it your way. My old employer wasn't very pleased when I had to tell him that he had to spin a 2000+ component, 16 layer, multi $1000 PCB because someone ::) had made a typo on a net name. The blind and buried net on the otherwise perfect board couldn't be reworked.
Cadence released a tool some years ago that allowed you to generate netlists from spreadsheets. Component,Pin, Netname. I don't think it's very popular for exactly the reasons I've given.
I think we may have to agree to differ.
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It is poor practice to force engineers to use CTRL F to hunt down each and every connection
But I never need to hunt down all connections. I just don't see how this is a use case for anyone. I'm typically interested in a few pins related to a part I'm working on at the moment.
Drawing the connectivity not only makes debug easier, it makes review easier too.
I guess it is a matter of taste then. Because that statement is false for me.
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It is poor practice to force engineers to use CTRL F to hunt down each and every connection
But I never need to hunt down all connections. I just don't see how this is a use case for anyone. I'm typically interested in a few pins related to a part I'm working on at the moment.
Of course you don't. It's your design, you know what's going on. Try working with a team of schematic engineers spread across the globe. Or try handing over your design to a team who don't understand it. The easier the schem is to read, the less they bother you...
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It's your design, you know what's going on.
As I said already, I don't design anything even remotely complicated. But I do have to work with schematics supplied by other people/companies. Some are very big. And most are designed in a way described by Eric_the_EE. I have no problems whatsoever getting information that I need from them.
The easier the schem is to read, the less they bother you...
The problem is in what you consider "easier". To me it is much easier to not see a clutter of connections. I'm not going to follow all of them with my finger. Even if they are there, I'll still just search for all the places where the signal of interest goes.
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If there are a clutter of connections, then the schematic has not been well drawn.
We must agree to differ.
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If there are a clutter of connections, then the schematic has not been well drawn.
We must agree to differ.
Cluttered connections cannot be avoided with some circuits/topologies. It is not simply a matter of layout, it is inherent in the connectivity. Not my bag but I think the mathematicians actually can classify networks in ways that demonstrate these differences.
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Ok, so I went back, and got rid of all the boxes. I used the Vcc and common ground symbols to eliminate wire-crossing as much as possible. I've rotated the SN754410 so that I didn't have to snake the X-axis motor signals around the bottom to get to the right side of the screen. I've also turned off the visible grid, and added a "no-connection" symbol to the unused pin on the trim pot.
Better? worse?
As a test of whether the schematic is able to convey the purpose of the circuit, can anyone guess what I'm trying to achieve with this circuit? Do you think it will work?
Thanks again for all of the input. It was very interesting to read all of the different PoVs on this subject.
Dave
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Better. But if VCC1 and VCC2 are connected, then why such complicated way to show this? Just put C1, C2 and C3 on the same level.
I would show R4 and R5 connected to VCC separately. Now it looks like there is some purpose for them to be connected to other pins of the IC.
IC symbol is drawn in a really weird way, which makes schematic capture more complicated than it needs to be. Bypass caps are least important for understaning of the functions, yet they are smack in the middle. Eliminate the whole block and move it outside.
There is also no need for all that white space on the right.
It looks like some sort of self balancing platform maybe? If the intent to have feedback-based system, then I'd say it will not work.
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Sometimes combinatorial interconnects are messy, and the best approach is to try to illustrate patterns.
I removed the power wiring and just used a node name. The op amp only needs power once, not in every unit.
I removed the decoupling and put it aside with a note explaining which part it's for.
The SN754410 got a custom component that better suits the schematic.
The motor output diodes were arranged in a pattern (again, for illustration).
The references don't match yours... I'm not THAT OCD. :D
(http://www.rockgarden.net/download/eevblog/schematic.png)
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That's great!
But if we are going for perfection, why not align comparators vertically?
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Ok, so I went back, and got rid of all the boxes. I used the Vcc and common ground symbols to eliminate wire-crossing as much as possible. I've rotated the SN754410 so that I didn't have to snake the X-axis motor signals around the bottom to get to the right side of the screen. I've also turned off the visible grid, and added a "no-connection" symbol to the unused pin on the trim pot.
Better? worse?
Usable.
Personally I would connect R3's "loose" end to the wiper, to minimise noise pickup. Using opamps as comparators can have surprising results, e.g. phase reversal.
The most important parts are the sensor inputs and motor outputs, so they should be on the far left and far right. The pots can then be nearer the comparators.
Power connector is given too much prominence; it can be confined to a corner somewhere, together with the board-level bulk decoupling capacitors. It is acceptable to not connect those with wires to each IC's power supply pins, but simply to use named nets.
U2's orientation is strange. Ideally rotate CW 90degrees, move the three inputs to the left and have the two outputs to the right, with the A inputs/outputs in the top half and the B inputs/outputs in the bottom half. That will emphasise the signal flow and that there are two identical sub-circuits.
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I didn't get nearly as much agreement as I expected about avoiding 4 way (cross) junctions. I'm surprised.
Maybe I should modify my advice to 'minimise'. For example, the +15V supply to V2. This could sensibly be moved left to that it forms a T junction above R4.
With regard to removing cross connections on the diodes creating "more mess". Simply move the bottom row of diodes to the right slightly and hey presto, all T junctions.
Maybe it's because I grew up in an era of 2nd or 3rd generation photocopies (and dyeline) but it's something that I religiously avoid.
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Gyro,
I completely agree. I didn't mention this as I thought it had been well covered.
Never ever make a connection at the intersection of four wires. It is too hard to spot the difference between this and a crossing without a connection.
When the wires meet at a T there is no room for confusion.
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Bson, thanks for the example. I'm filing this away for future reference.
The op amp only needs power once, not in every unit.
I connected them all in an attempt to work around an apparent bug in EasyEDA's PCB module. For some reason connecting just one op-amp to power and ground resulted in the ground pin of the LM324 not being connected to any net.
Dave
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[...]
The SN754410 got a custom component that better suits the schematic.
[...]
Bingo. How often do folks make their own schematic components?
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Bingo. How often do folks make their own schematic components?
I do make mine, but once, not for each schematic. I prefer to think and figure out what will work for most use cases.
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I didn't get nearly as much agreement as I expected about avoiding 4 way (cross) junctions. I'm surprised.
I would agree that in some cases it may cause confusion, but not everywhere. Here you have an example of a circuit that will make no sense if all diodes are attached, and depicted circuit is very typical.
I really see no need to complicate things here.
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[...]
The SN754410 got a custom component that better suits the schematic.
[...]
Bingo. How often do folks make their own schematic components?
As often as is beneficial. The proportion depends on the type of component: 100% for FPGAs/CPLDs, 0% for standard logic and standard opamps/comparators/R/L/C, very variable for "special purpose" ICs such as motor controllers.
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I didn't get nearly as much agreement as I expected about avoiding 4 way (cross) junctions. I'm surprised.
I would agree that in some cases it may cause confusion, but not everywhere. Here you have an example of a circuit that will make no sense if all diodes are attached, and depicted circuit is very typical.
I really see no need to complicate things here.
Surprise, surprise we disagree again! :D
There's no confusion in this case, but there is still room for mistake. One missing junction dot and you're looking at a board spin.
Please don't do it OP, it is widely considered to be bad practice.
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I completely agree ( >:D ).
I can't think of a single case where I've needed to connect on a cross, there is simply no need to do it.
Referring to bson's recent schematic, having +15V going through a cross connection to U2 Pin 16 (VCC1) is an instant fail, too open to errors. As I said previously on motor output clamp diode, moving the upper row left or the lower row right would eliminate cross connections with zero loss of clarity and lower risk of schematic error.
Sorry but it's a cardinal rule with me (and I think most people), both composing and reviewing.
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Surprise, surprise we disagree again! :D
There's no confusion in this case, but there is still room for mistake. One missing junction dot and you're looking at a board spin.
Please don't do it OP, it is widely considered to be bad practice.
I am also in agreement with you.
There is another reason (although lately is less important): making copies. Small dots may be obliterated, and dirt could be also confused as a connection.
A T-connection is the best practice.... And since this topic is about best practices, I think this advice should be heeded.
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Ok one more try. Sorry to :horse:, but I think I've taken everyone's suggestions to heart. I created a custom footprint for the SN754410. I moved the power connector and the decoupling capacitors into a separate block. Sensors are on the far left, so signals travel left-to-right. Motor outputs are on the far right and I've only connected VCC and GND to the op-amp once. I've tied the loose end of the pot to the wiper to reduce noise.
Let me know what you think.
Thanks,
Dave
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I don't understand why you try to avoid power supply symbols. Why do you need those 4 parallel lines on the bottom? Why all those lines going to the diodes?
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I've fixed D2/D3 for you. Do you see what we mean about not making a connection at a 4 way intersection?