The problem is not breadboarding per se, but it must be used responsibly.
Not terribly, terribly much has changed in CMOS since the 90s; the main difference being, bog-standard logic is indeed faster. You might've been used to 74/LS TTL, or CD4000 CMOS, neither of which is prone to signal quality issues. (The latter basically at all, ever; the former can be, but is often tolerant of poor conditions.)
Whereas today, the average 3.3V CMOS pin driver, is somewhere between 74HC and LVC families, in terms of speed and drive strength. Edges of 1-3ns and source impedance of 30-100 ohms is typical. You don't need fancy MCUs to get there: you can see signal quality issues on a breadboard, even with a boring old 5V ATMEGA328 (Arduino, etc.) running at 20MHz.
So you might well have spent time with these sorts of circuits back then, and never noticed these effects. Or you simply don't remember -- and honestly I can't remember a whole lot from that long ago, nothing wrong with that.
As for probing, avoid ground-return length. The signal is likely nice and square at the device itself. Try probing between its GND and output pins. And BTW, it's not supply bounce (poor bypassing), notice it's symmetrical -- if it were that, it should only be doing it on the top. But in any case, make sure there's a bypass cap at the device, between nearest VDD/GND pins; if need be, span it over the chip, since you can get away with moves like that on the breadboard.
The same goes for anything else that connects to the device. If local switching currents (from each respective chip) are well contained, then you only have to deal with pin/wire currents, and those can be limited with series resistance (preferably 33 ohms or more, as close to the driving pin as possible -- if a shared bus, this applies to every driver!). Or for longer wires/jumpers, a ferrite bead perhaps (same idea, resistance at high frequency).
The supply rails on a breadboard, are pretty thin and narrow, they're easily driven to some voltage at high frequencies -- 100s of mV of ground bounce is easily produced by a chip. Keep distances short (between VDD/GND, use adjacent pairs not opposite, around a row of ICs), try to avoid lots of signals switching all at once (parallel buses with fast edge rates are killer; many a breadboarded computer, even just with TTL or NMOS (e.g. 6502, Z80, etc.), had random glitches, likely due to this). Which is nice again these days, as serial buses (I2C, SPI) are predominant, parallel buses only being needed for legacy interface, or the highest bandwidths (memory, display drivers, etc.).
Or it can still simply be scope/probe effect. There's often a high frequency compensation adjustment, and maybe it's out of whack, or the probe is mismatched to this scope. (This is probably more of an analog scope issue, and I don't think DSOs usually have this as a problem; but equally so, I don't think they usually have an adjustment for it. I guess that should put the blame on the probe -- maybe try one recommended by the scope manufacturer?) I guess a reference source would be needed to confirm. As for the TDS210, they're pretty slow and chunky, you might simply not be seeing it, whether at this zoom (gotta get a close-up of the edge) or in general (60MHz BW?).
Tim
Home
Help
Search
Login
Register
